SPI_DEVICE/2P Simulation Results

Wednesday September 24 2025 17:31:32 UTC

GitHub Revision: ce6e476

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	43.360s	26.638ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.210s	30.268us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.980s	357.331us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	26.070s	9.039ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	9.270s	220.287us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.740s	299.489us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.980s	357.331us	1	1	100.00
		spi_device_csr_aliasing	9.270s	220.287us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	12.047us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.060s	19.843us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.920s	18.231us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.060s	41.666us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	0.840s	36.718us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	1.630s	659.305us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.630s	659.305us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.950s	59.963ms	1	1	100.00
		spi_device_tpm_sts_read	1.140s	339.402us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	24.120s	6.260ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.300s	5.299ms	1	1	100.00
		spi_device_flash_all	2.111m	60.844ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.220s	2.971ms	1	1	100.00
		spi_device_flash_all	2.111m	60.844ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.220s	2.971ms	1	1	100.00
		spi_device_flash_all	2.111m	60.844ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	2.111m	60.844ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	5.220s	2.879ms	1	1	100.00
		spi_device_flash_all	2.111m	60.844ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	5.220s	2.879ms	1	1	100.00
		spi_device_flash_all	2.111m	60.844ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	5.220s	2.879ms	1	1	100.00
		spi_device_flash_all	2.111m	60.844ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	5.220s	2.879ms	1	1	100.00
		spi_device_flash_all	2.111m	60.844ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	5.220s	2.879ms	1	1	100.00
		spi_device_flash_all	2.111m	60.844ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	13.120s	7.398ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	1.033m	11.973ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.033m	11.973ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.033m	11.973ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	2.370s	85.143us	1	1	100.00
		spi_device_read_buffer_direct	3.710s	353.287us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.033m	11.973ms	1	1	100.00
		spi_device_flash_all	2.111m	60.844ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	2.111m	60.844ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	2.111m	60.844ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	1.940s	124.008us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	1.940s	124.008us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	43.360s	26.638ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.056m	4.008ms	1	1	100.00
V2	stress_all	spi_device_stress_all	22.340s	2.380ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.730s	125.075us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.710s	13.465us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	1.680s	938.268us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	1.680s	938.268us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.210s	30.268us	1	1	100.00
		spi_device_csr_rw	1.980s	357.331us	1	1	100.00
		spi_device_csr_aliasing	9.270s	220.287us	1	1	100.00
		spi_device_same_csr_outstanding	3.060s	399.162us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.210s	30.268us	1	1	100.00
		spi_device_csr_rw	1.980s	357.331us	1	1	100.00
		spi_device_csr_aliasing	9.270s	220.287us	1	1	100.00
		spi_device_same_csr_outstanding	3.060s	399.162us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	0.970s	47.376us	1	1	100.00
		spi_device_tl_intg_err	15.980s	4.117ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	15.980s	4.117ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	30.930s	13.479ms	1	1	100.00
		TOTAL			33	33	100.00