SRAM_CTRL/MAIN Simulation Results

Wednesday September 24 2025 17:31:32 UTC

GitHub Revision: ce6e476

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	42.740s	3.231ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.940s	23.093us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.940s	33.547us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.460s	234.060us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.840s	15.675us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.190s	350.547us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.940s	33.547us	1	1	100.00
		sram_ctrl_csr_aliasing	0.840s	15.675us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.190m	21.109ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.055m	5.235ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	13.929m	20.098ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.816m	34.928ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	8.295m	166.303ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	14.587m	14.165ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	45.170s	22.003ms	1	1	100.00
V2	executable	sram_ctrl_executable	10.785m	67.984ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	17.440s	2.130ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.212m	13.275ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	43.480s	1.029ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	46.650s	3.093ms	1	1	100.00
		sram_ctrl_throughput_w_readback	33.110s	5.514ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.082m	10.227ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.440s	1.210ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	56.248m	581.223ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.960s	15.573us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.150s	50.478us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.150s	50.478us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.940s	23.093us	1	1	100.00
		sram_ctrl_csr_rw	0.940s	33.547us	1	1	100.00
		sram_ctrl_csr_aliasing	0.840s	15.675us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.090s	41.706us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.940s	23.093us	1	1	100.00
		sram_ctrl_csr_rw	0.940s	33.547us	1	1	100.00
		sram_ctrl_csr_aliasing	0.840s	15.675us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.090s	41.706us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	18.460s	7.392ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.940s	1.036us	0	1	0.00
		sram_ctrl_tl_intg_err	1.770s	141.443us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.940s	1.036us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.770s	141.443us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.082m	10.227ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.082m	10.227ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.940s	33.547us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	10.785m	67.984ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	10.785m	67.984ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	10.785m	67.984ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	45.170s	22.003ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.690s	2.781ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	18.460s	7.392ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	6.630s	690.829us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	42.740s	3.231ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	42.740s	3.231ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	10.785m	67.984ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.940s	1.036us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	45.170s	22.003ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.940s	1.036us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.940s	1.036us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	42.740s	3.231ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.940s	1.036us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.147m	2.421ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.42354471552844202203617236762407964857309172832277992298732755376137074174294
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 690829197 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x68) != exp (0x7c)
        UVM_INFO @ 690829197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.29324425708661863044908598414195102567929024969803484839239182217747093480876
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   1035767 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   1035767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---