SRAM_CTRL/RET Simulation Results

Wednesday September 24 2025 17:31:32 UTC

GitHub Revision: ce6e476

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.260s	631.328us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.630s	46.447us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.690s	21.855us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.650s	134.995us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.740s	27.397us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	0.970s	98.977us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.690s	21.855us	1	1	100.00
		sram_ctrl_csr_aliasing	0.740s	27.397us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.630s	354.845us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.210s	102.330us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	7.652m	10.182ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.245m	51.009ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	27.800s	3.833ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	2.416m	6.644ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.340s	977.911us	1	1	100.00
V2	executable	sram_ctrl_executable	5.745m	10.448ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	51.640s	2.444ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.076m	6.768ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	4.880s	78.822us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	4.410s	355.389us	1	1	100.00
		sram_ctrl_throughput_w_readback	7.060s	267.385us	1	1	100.00
V2	regwen	sram_ctrl_regwen	12.400s	1.587ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.700s	63.325us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	8.576m	4.358ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.660s	99.603us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.670s	87.769us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.670s	87.769us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.630s	46.447us	1	1	100.00
		sram_ctrl_csr_rw	0.690s	21.855us	1	1	100.00
		sram_ctrl_csr_aliasing	0.740s	27.397us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.750s	51.278us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.630s	46.447us	1	1	100.00
		sram_ctrl_csr_rw	0.690s	21.855us	1	1	100.00
		sram_ctrl_csr_aliasing	0.740s	27.397us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.750s	51.278us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.300s	2.429ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.610s	3.497us	0	1	0.00
		sram_ctrl_tl_intg_err	1.260s	313.192us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.610s	3.497us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.260s	313.192us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	12.400s	1.587ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	12.400s	1.587ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.690s	21.855us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.745m	10.448ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.745m	10.448ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.745m	10.448ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.340s	977.911us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.850s	36.386us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.300s	2.429ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.940s	115.634us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.260s	631.328us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.260s	631.328us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.745m	10.448ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.610s	3.497us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.340s	977.911us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.610s	3.497us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.610s	3.497us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.260s	631.328us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.610s	3.497us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	15.910s	3.163ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.18688822126913993411085318158478516836172317907112365328368669215845192672382
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3496980 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3496980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---