SYSRST_CTRL Simulation Results

Wednesday September 24 2025 17:31:32 UTC

GitHub Revision: ce6e476

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	4.600s	2.112ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	1.840s	2.479ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	1.710s	2.290ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	5.910s	2.545ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	11.290s	6.043ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	4.280s	2.074ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	38.120s	75.281ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	3.800s	2.703ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	4.860s	2.067ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	4.280s	2.074ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	3.800s	2.703ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	33.920s	67.594ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	38.750s	74.857ms	0	1	0.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	1.796m	116.307ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	5.080s	5.488ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	1.650s	2.529ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	0.990s	2.176ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	1.064m	306.174ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	1.660s	2.624ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	2.950s	4.311ms	1	1	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.286m	37.593ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	1.945m	258.809ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	1.570s	2.031ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	1.580s	2.018ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	2.560s	2.291ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	2.560s	2.291ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	11.290s	6.043ms	1	1	100.00
		sysrst_ctrl_csr_rw	4.280s	2.074ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	3.800s	2.703ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	6.920s	4.536ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	11.290s	6.043ms	1	1	100.00
		sysrst_ctrl_csr_rw	4.280s	2.074ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	3.800s	2.703ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	6.920s	4.536ms	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	sysrst_ctrl_sec_cm	39.910s	22.009ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	6.350s	23.063ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	6.350s	23.063ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	6.500s	11.821ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 1 failures:
  • Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

    • 0.sysrst_ctrl_combo_detect_with_pre_cond.114508034925811899285672640386220990922440100773489438060143441471952875435376
      Line 402, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

        UVM_ERROR @ 26080183852 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 26200183852 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
        UVM_INFO @ 26220183852 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
        UVM_INFO @ 36361902205 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2b
        UVM_INFO @ 36361982205 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x1f