UART Simulation Results

Wednesday September 24 2025 17:31:32 UTC

GitHub Revision: ce6e476

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	0.990s	844.285us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.890s	14.100us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.810s	31.197us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.940s	57.718us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.670s	21.398us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.010s	43.927us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.810s	31.197us	1	1	100.00
		uart_csr_aliasing	0.670s	21.398us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	34.410s	32.076ms	1	1	100.00
V2	parity	uart_smoke	0.990s	844.285us	1	1	100.00
		uart_tx_rx	34.410s	32.076ms	1	1	100.00
V2	parity_error	uart_intr	12.500s	27.794ms	1	1	100.00
		uart_rx_parity_err	39.320s	28.156ms	1	1	100.00
V2	watermark	uart_tx_rx	34.410s	32.076ms	1	1	100.00
		uart_intr	12.500s	27.794ms	1	1	100.00
V2	fifo_full	uart_fifo_full	31.240s	30.667ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.368m	153.144ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	34.330s	46.253ms	1	1	100.00
V2	rx_frame_err	uart_intr	12.500s	27.794ms	1	1	100.00
V2	rx_break_err	uart_intr	12.500s	27.794ms	1	1	100.00
V2	rx_timeout	uart_intr	12.500s	27.794ms	1	1	100.00
V2	perf	uart_perf	2.031m	13.423ms	1	1	100.00
V2	sys_loopback	uart_loopback	10.930s	6.435ms	1	1	100.00
V2	line_loopback	uart_loopback	10.930s	6.435ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	8.710s	5.097ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	11.350s	38.321ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	11.360s	6.755ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	5.500s	1.576ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	10.602m	122.233ms	1	1	100.00
V2	stress_all	uart_stress_all	8.887m	91.767ms	0	1	0.00
V2	alert_test	uart_alert_test	0.790s	24.891us	1	1	100.00
V2	intr_test	uart_intr_test	0.650s	13.913us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.090s	109.016us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.090s	109.016us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.890s	14.100us	1	1	100.00
		uart_csr_rw	0.810s	31.197us	1	1	100.00
		uart_csr_aliasing	0.670s	21.398us	1	1	100.00
		uart_same_csr_outstanding	0.850s	27.358us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.890s	14.100us	1	1	100.00
		uart_csr_rw	0.810s	31.197us	1	1	100.00
		uart_csr_aliasing	0.670s	21.398us	1	1	100.00
		uart_same_csr_outstanding	0.850s	27.358us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.160s	39.751us	1	1	100.00
		uart_tl_intg_err	0.840s	55.427us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	0.840s	55.427us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	46.140s	15.681ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:
  • Test uart_stress_all has 1 failures.

    • 0.uart_stress_all.24707453476482593211947279818465627972490093404673910137066524719487205736592
      Line 81, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        UVM_ERROR @ 91025644203 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 91025644203 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 91348344203 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 5,                                 clk_pulses: 0
        UVM_ERROR @ 91419594203 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 10,                                 clk_pulses: 0
        UVM_ERROR @ 91419606703 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty