CHIP Simulation Results

Wednesday September 24 2025 17:31:32 UTC

GitHub Revision: `ce6e476`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.654m	2.904ms	1	1	100.00
		chip_sw_example_rom	1.365m	2.726ms	1	1	100.00
		chip_sw_example_manufacturer	2.220m	3.496ms	1	1	100.00
		chip_sw_example_concurrency	3.019m	3.069ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.535m	5.449ms	1	1	100.00
V1	csr_rw	chip_csr_rw	6.930m	6.261ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	2.752m	3.114ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.035h	28.596ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	1.021m	2.515ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.035h	28.596ms	1	1	100.00
		chip_csr_rw	6.930m	6.261ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.640s	194.207us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.701m	4.670ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.701m	4.670ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.701m	4.670ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.611m	4.056ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.611m	4.056ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.501m	3.686ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.116m	4.402ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.474m	4.080ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	15.298m	7.847ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	6.802m	4.995ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	18.970m	12.986ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.715m	5.504ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.715m	5.504ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.431m	2.628ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.850m	3.499ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.099m	3.314ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	12.097m	11.873ms	1	1	100.00
		chip_tap_straps_testunlock0	1.589m	2.721ms	1	1	100.00
		chip_tap_straps_rma	3.706m	4.460ms	1	1	100.00
		chip_tap_straps_prod	1.556m	1.986ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.735m	2.992ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.212m	8.409ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.439m	4.873ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.439m	4.873ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.863m	7.770ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	39.652m	21.175ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.785m	4.550ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.068m	5.936ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	56.379m	18.672ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.909m	2.463ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.832m	5.641ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.995m	2.709ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	17.115m	9.954ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.187m	2.829ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.522m	5.316ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.477m	2.853ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.502m	2.757ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	9.399m	9.470ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.806m	5.149ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	3.124m	3.421ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.806m	5.149ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.467m	2.180ms	1	1	100.00
		chip_sw_aes_smoketest	2.770m	3.266ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.649m	3.548ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.750m	3.539ms	1	1	100.00
		chip_sw_csrng_smoketest	2.739m	2.261ms	1	1	100.00
		chip_sw_entropy_src_smoketest	13.659m	7.016ms	1	1	100.00
		chip_sw_gpio_smoketest	3.171m	3.346ms	1	1	100.00
		chip_sw_hmac_smoketest	2.930m	2.515ms	1	1	100.00
		chip_sw_kmac_smoketest	2.459m	3.154ms	1	1	100.00
		chip_sw_otbn_smoketest	12.168m	6.855ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.820m	5.835ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.957m	5.663ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.429m	3.256ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.238m	2.443ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.363m	3.028ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.198m	2.453ms	1	1	100.00
		chip_sw_uart_smoketest	2.158m	2.360ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.556m	3.477ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.826m	4.907ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.194h	60.984ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	41.368m	14.942ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.623m	5.597ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.824m	2.660ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.574m	3.808ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.010h	53.329ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.114h	57.763ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.296m	3.034ms	1	1	100.00
V2	tl_d_illegal_access	chip_tl_errors	2.296m	3.034ms	1	1	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.035h	28.596ms	1	1	100.00
		chip_same_csr_outstanding	46.194m	30.913ms	1	1	100.00
		chip_csr_hw_reset	3.535m	5.449ms	1	1	100.00
		chip_csr_rw	6.930m	6.261ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.035h	28.596ms	1	1	100.00
		chip_same_csr_outstanding	46.194m	30.913ms	1	1	100.00
		chip_csr_hw_reset	3.535m	5.449ms	1	1	100.00
		chip_csr_rw	6.930m	6.261ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	25.920s	491.953us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	3.980s	39.435us	1	1	100.00
		xbar_smoke_large_delays	1.107m	10.674ms	1	1	100.00
		xbar_smoke_slow_rsp	36.190s	3.888ms	1	1	100.00
		xbar_random_zero_delays	15.630s	290.243us	1	1	100.00
		xbar_random_large_delays	2.516m	23.866ms	1	1	100.00
		xbar_random_slow_rsp	3.253m	22.612ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	34.510s	1.386ms	1	1	100.00
		xbar_error_and_unmapped_addr	27.040s	1.125ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	21.290s	422.671us	1	1	100.00
		xbar_error_and_unmapped_addr	27.040s	1.125ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	8.560s	125.498us	1	1	100.00
		xbar_access_same_device_slow_rsp	2.069m	14.293ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	9.920s	443.835us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	22.460s	1.068ms	1	1	100.00
		xbar_stress_all_with_error	1.220m	1.416ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	1.580m	287.396us	1	1	100.00
		xbar_stress_all_with_reset_error	3.176m	2.581ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	41.368m	14.942ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	37.049m	29.397ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	41.603m	15.094ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	33.730m	10.764ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	42.514m	15.877ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	42.237m	17.556ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	42.737m	15.826ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	42.655m	15.877ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	16.600s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	21.790s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	18.260s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	17.580s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	20.700s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	17.020s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	19.980s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	19.150s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	17.000s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	17.240s	10.360us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	20.240s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	16.560s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	17.100s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	16.630s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	19.310s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	20.930s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	17.120s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	22.160s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	16.480s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	17.900s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	19.310s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	18.560s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.790s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	15.930s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.810s	10.380us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	31.671m	11.248ms	1	1	100.00
		rom_e2e_asm_init_dev	42.462m	15.277ms	1	1	100.00
		rom_e2e_asm_init_prod	42.752m	15.598ms	1	1	100.00
		rom_e2e_asm_init_prod_end	40.853m	16.285ms	1	1	100.00
		rom_e2e_asm_init_rma	41.378m	14.374ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	40.702m	15.379ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	40.619m	14.879ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	39.348m	15.906ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	43.914m	17.814ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	51.245m	34.605ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	51.245m	34.605ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.897m	2.638ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.909m	2.463ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.092m	2.972ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.072m	2.913ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	26.866m	12.415ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.594m	3.189ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.123m	4.573ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.859m	4.224ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	10.036m	5.568ms	1	1	100.00
		chip_plic_all_irqs_10	5.174m	3.228ms	1	1	100.00
		chip_plic_all_irqs_20	6.163m	4.164ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.916m	2.781ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	14.195m	8.798ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.494m	3.013ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.956m	3.116ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.991m	7.101ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	18.146m	7.828ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.575m	7.214ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.364h	255.280ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.580m	4.165ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.820m	5.835ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.580m	4.165ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.957m	10.504ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.957m	10.504ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.970m	6.247ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.146m	5.409ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.585m	6.365ms	1	1	100.00
		chip_sw_aes_idle	2.072m	2.913ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.248m	3.303ms	1	1	100.00
		chip_sw_kmac_idle	3.330m	3.492ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.430m	3.687ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.849m	4.262ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	5.664m	5.111ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.228m	4.070ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	12.607m	11.914ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.054m	3.991ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.646m	4.322ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.183m	3.315ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.485m	5.334ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.952m	4.377ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.882m	4.915ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.863m	7.770ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	10.033m	9.493ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.183m	3.315ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.485m	5.334ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.785m	4.550ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.068m	5.936ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	56.379m	18.672ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.909m	2.463ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.832m	5.641ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.995m	2.709ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	17.115m	9.954ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.187m	2.829ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.522m	5.316ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.477m	2.853ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.652m	2.629ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.389m	4.763ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.733m	7.385ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	49.824m	25.263ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.322m	2.609ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.193m	3.021ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	15.577m	9.240ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.875m	3.065ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.989m	3.885ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	20.114m	22.293ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	3.811h	169.391ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.863m	7.770ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	6.367m	4.896ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.938m	3.195ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.859m	4.224ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	14.991m	7.101ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.664m	5.571ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	4.583m	5.384ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.806m	6.192ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.132m	2.948ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	50.505m	17.199ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.683m	3.364ms	1	1	100.00
		chip_sw_edn_entropy_reqs	11.613m	5.574ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.683m	3.364ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.664m	5.571ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.480m	2.662ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	18.095m	21.902ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.113m	5.342ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.068m	5.936ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.841m	3.516ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.785m	4.550ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.011h	44.090ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	18.095m	21.902ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.057m	2.875ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	12.917m	6.808ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.188m	4.505ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.011h	44.090ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.188m	4.505ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.188m	4.505ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.188m	4.505ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.188m	4.505ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.859m	4.224ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.293m	4.576ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.472m	5.282ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.756m	5.738ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.756m	5.738ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.663m	2.229ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.995m	2.709ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.248m	3.303ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.345m	2.674ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.708m	3.816ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.297m	4.683ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	7.101m	5.511ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.082m	4.897ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	6.485m	4.254ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	12.917m	6.808ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	17.115m	9.954ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	29.476m	12.529ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	26.866m	12.415ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	39.565m	13.086ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.058m	3.015ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.079m	2.954ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.187m	2.829ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	12.917m	6.808ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	12.176m	13.041ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.282m	2.530ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	9.881m	4.647ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.330m	3.492ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.123m	4.573ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	12.097m	11.873ms	1	1	100.00
		chip_tap_straps_rma	3.706m	4.460ms	1	1	100.00
		chip_tap_straps_prod	1.556m	1.986ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.363m	2.440ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	12.176m	13.041ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	12.176m	13.041ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	12.176m	13.041ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	22.123m	10.808ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.188m	4.505ms	1	1	100.00
		chip_sw_flash_rma_unlocked	1.011h	44.090ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.867m	2.903ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.658m	7.455ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.952m	6.307ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	10.422m	8.348ms	1	1	100.00
		chip_sw_lc_ctrl_transition	12.176m	13.041ms	1	1	100.00
		chip_sw_keymgr_key_derivation	12.917m	6.808ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.909m	10.073ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	8.118m	7.629ms	1	1	100.00
		chip_prim_tl_access	1.293m	4.576ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	10.033m	9.493ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.054m	3.991ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.646m	4.322ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.183m	3.315ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.485m	5.334ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.952m	4.377ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.882m	4.915ms	1	1	100.00
		chip_tap_straps_dev	12.097m	11.873ms	1	1	100.00
		chip_tap_straps_rma	3.706m	4.460ms	1	1	100.00
		chip_tap_straps_prod	1.556m	1.986ms	1	1	100.00
		chip_rv_dm_lc_disabled	53.950s	2.739ms	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.357m	3.540ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.298m	2.755ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.390m	2.957ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.591m	3.431ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	18.533m	24.668ms	1	1	100.00
		chip_rv_dm_lc_disabled	53.950s	2.739ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.068h	50.343ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.133h	46.259ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.739m	8.733ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.110h	47.641ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	18.533m	24.668ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.068m	2.995ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.128m	2.728ms	1	1	100.00
		rom_volatile_raw_unlock	1.214m	2.692ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	56.295m	16.839ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	56.379m	18.672ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.585m	6.365ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.585m	6.365ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.585m	6.365ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.870m	4.435ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	12.176m	13.041ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	18.095m	21.902ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.870m	4.435ms	1	1	100.00
		chip_sw_keymgr_key_derivation	12.917m	6.808ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.665m	5.457ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.256m	2.653ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	18.095m	21.902ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.870m	4.435ms	1	1	100.00
		chip_sw_keymgr_key_derivation	12.917m	6.808ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.665m	5.457ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.256m	2.653ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	12.176m	13.041ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	6.431m	4.436ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.363m	2.440ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.867m	2.903ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.658m	7.455ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.952m	6.307ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	10.422m	8.348ms	1	1	100.00
		chip_sw_lc_ctrl_transition	12.176m	13.041ms	1	1	100.00
		chip_prim_tl_access	1.293m	4.576ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.293m	4.576ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	17.235m	9.330ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.015m	8.050ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	15.801m	25.081ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.113m	7.487ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.059m	8.121ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.119m	6.851ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	16.506m	22.468ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	17.192m	14.641ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	8.957m	10.504ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	10.995m	13.234ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	6.054m	4.268ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.015m	8.050ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	2.932m	3.506ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	42.634m	29.710ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.816m	5.177ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.892m	5.359ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	25.576m	25.614ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.073m	6.864ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	14.171m	9.759ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	20.014m	30.046ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.275m	2.650ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.859m	4.224ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.909m	10.073ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.909m	10.073ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	14.171m	9.759ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	25.576m	25.614ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	6.054m	4.268ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.820m	5.835ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.787m	4.138ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.146m	3.571ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	5.966m	5.522ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	14.195m	8.798ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.611m	2.899ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.859m	4.224ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	18.146m	7.828ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.881m	4.040ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.505m	4.410ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.379m	3.432ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.256m	2.653ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.146m	3.571ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.146m	3.571ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	16.044m	13.831ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	13.264m	13.443ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.787m	4.138ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.977m	4.433ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.005m	5.757ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.706m	4.460ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	53.950s	2.739ms	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	10.036m	5.568ms	1	1	100.00
		chip_plic_all_irqs_10	5.174m	3.228ms	1	1	100.00
		chip_plic_all_irqs_20	6.163m	4.164ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.867m	2.485ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	3.022m	2.692ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	41.368m	14.942ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.458m	5.490ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.580m	3.165ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.661m	3.665ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.991m	3.057ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.665m	5.457ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.522m	5.316ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	4.966m	6.242ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.098m	6.790ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	8.118m	7.629ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.859m	4.224ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.439m	4.873ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.073m	6.864ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	20.295m	25.396ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	1.918m	2.345ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.591m	3.801ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	6.311m	4.755ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	20.295m	25.396ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	20.295m	25.396ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	38.374m	19.983ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	38.374m	19.983ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.862m	5.531ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	51.245m	34.605ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.190m	2.854ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.214m	2.849ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.487m	3.419ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	6.441m	4.278ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	18.158m	8.377ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.407h	31.393ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	30.755m	12.038ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.720m	3.224ms	1	1	100.00
V2		TOTAL			238	275	86.55
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.133m	3.660ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.849m	2.776ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.553h	71.796ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	5.841m	3.359ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	19.018m	11.890ms	1	1	100.00
		rom_e2e_jtag_debug_dev	17.572m	10.076ms	1	1	100.00
		rom_e2e_jtag_debug_rma	19.238m	11.920ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.700m	3.975ms	1	1	100.00
		rom_e2e_jtag_inject_dev	4.365m	5.550ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.397m	4.626ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.192s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.274m	5.700ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.678m	2.924ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	11.225m	4.567ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	18.296m	8.694ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.529m	2.473ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.920m	5.294ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.526m	2.841ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.032m	6.241ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.966m	6.447ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.840m	4.879ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	14.171m	9.759ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	19.018m	11.890ms	1	1	100.00
		rom_e2e_jtag_debug_dev	17.572m	10.076ms	1	1	100.00
		rom_e2e_jtag_debug_rma	19.238m	11.920ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.971m	4.276ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.859m	4.224ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.580h	37.881ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.580h	37.881ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	3.246m	3.176ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.611m	4.056ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	49.988m	18.289ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.608m	3.192ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.635m	5.073ms	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	31.512m	21.768ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	1.785m	2.097ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.669m	2.536ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	4.156m	3.846ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	12.534s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.060m	3.314ms	1	1	100.00
		TOTAL			283	326	86.81

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.61856778841965626552289810247750025057475706305220904044389451572265225150281
    Line 468, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.64623307525932439807706764263454310819689740867114590205308194393438220769677
    Line 529, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.100462853816957617151701437362699002285454398468043417756768859275137785660774
    Line 536, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.100467794366407385390203838240398844822476720186389275139416928903523097464040
    Line 526, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.20323749307591689011019233209653030900022774537622426242317978392664494882106
    Line 523, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.59723856910967815669122658706311605463163572102278938156733439731575440363015
    Line 488, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.111706777519252805600040479120777327206724146772993244909568072240151921888861
    Line 487, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.34008273191706571428657431418295383479226131930864940825805001572285251351174
    Line 486, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.53033540411607002536897237234648847393650309478192747790970101674086996258929
    Line 496, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.22455255097841385612504266601868059569251350423933021431322882530279742482797
    Line 494, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.100409488001091481001053479505598655672823291334524027603925119448199818515602
    Line 490, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.21337895416826406952488677910603932014781948967188399510619201282219301113116
    Line 530, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.10104802373025133474909121523687999538135231009585795442500022601762409433330
    Line 482, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.38649866481624044052767942720872739187081841051015432049477053943699896289960
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.157s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.62660227526726230583523488824713617766741926802850256023075448496258526731991
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.132s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.25127835508959464614854716302425456401707307449938678285401208019733632360467
    Line 537, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.24718825909551340244153642140431092147019147854391314667573201209819430053273
    Line 481, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.110893929170460072723273381837071953972034404351234846123893727006103947343467
    Line 581, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.41647439926169475821846761193426103729180506949288516023973794099828417531335
    Line 494, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.61501495752418081641630403053452025278558522344004150892692857312892157857152
    Line 573, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 2628.281000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 2628.281000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.8500604140020324026329405413720156266668586713553681184914027918775336540028
    Line 403, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3164.642330 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3164.642330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.81534786113762476380210290566273200777865485558495331201315873585128909712642
    Line 423, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 21768.196677 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 21768.196677 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78292) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.114306083454441744001383857868419644957173563674040215016918754846757101290513
Line 415, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3571.045130 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78292) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3571.045130 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.6361703523345669044859798448045011886250689712164588134541276213065332011553
    Line 417, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34605.014307 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34605.014307 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.97327443030661904015713801970343783618465053704950611752966391638915406303317
    Line 387, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3189.455104 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3189.455104 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1330464529625678173006393228359521746212760236903766790637965824788417139170
    Line 388, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3115.746612 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3115.746612 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.79579505452261743097264930401887604564085260481667794159273163876105557305650
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.45739557348000420804586395744508113522864391915368501908891211751329163447438
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2673.838870 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2673.838870 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.94230978422511283587805890171014460783671723418861247764210217717816245982092
    Line 199, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 2738.666665 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10670 read out mismatch
  UVM_INFO @ 2738.666665 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.64380620527739658583363346178074856291118884091713209191029957384468241872958
    Line 405, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2775.815435 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2775.815435 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.17637003575188784274807507679679923971940737654579634087182938530489003051617
    Line 404, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 2659.826000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2659.826000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.64257279627104756034460954267043691505723346905750467217726653155412347663387
    Line 415, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3807.840500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3807.840500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.80580896283175235404189206875484899883984506720562894440885119559065873556982
    Line 425, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 21175.237710 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 21175.237710 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.90859365364703220347954706112218111315238708111024745114950860860706068303285
    Line 451, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3358.715052 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3358.715052 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.70316595002282563782687515762979865885393374994263210752617218763591077117097
    Line 504, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.64689247139491408369536119667748577828938616722097727166223312433598149185789
    Line 496, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32876) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.7863887559993936000960633869668021539332534228324336799391162264829497038427
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2515.182220 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32876) { a_addr: 'h10410  a_data: 'hf1dfb64  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h21  a_opcode: 'h4  a_user: 'h1b12c  d_param: 'h0  d_source: 'h21  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2515.182220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---