ADC_CTRL Simulation Results

Thursday September 25 2025 19:17:05 UTC

GitHub Revision: 8f374b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	3.290s	5.611ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.610s	943.691us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.420s	377.323us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	44.130s	26.429ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.890s	1.156ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.780s	514.055us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.420s	377.323us	1	1	100.00
		adc_ctrl_csr_aliasing	2.890s	1.156ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	1.834m	482.208ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	8.031m	479.426ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	4.344m	325.673ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	9.183m	332.520ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	3.787m	569.682ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	5.154m	200.844ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	4.960m	166.016ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	2.545m	336.216ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.420s	3.732ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.143m	38.038ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	2.687m	101.793ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	1.888m	256.837ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.170s	353.286us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.180s	293.724us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.310s	567.387us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.310s	567.387us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.610s	943.691us	1	1	100.00
		adc_ctrl_csr_rw	1.420s	377.323us	1	1	100.00
		adc_ctrl_csr_aliasing	2.890s	1.156ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.860s	2.083ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.610s	943.691us	1	1	100.00
		adc_ctrl_csr_rw	1.420s	377.323us	1	1	100.00
		adc_ctrl_csr_aliasing	2.890s	1.156ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.860s	2.083ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	5.050s	8.598ms	1	1	100.00
		adc_ctrl_tl_intg_err	25.130s	8.413ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	25.130s	8.413ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	4.620s	24.331ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00