AES/MASKED Simulation Results

Thursday September 25 2025 19:17:05 UTC

GitHub Revision: 8f374b4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	60.602us	1	1	100.00
V1	smoke	aes_smoke	3.000s	70.627us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	1.000s	61.884us	1	1	100.00
V1	csr_rw	aes_csr_rw	1.000s	85.845us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	3.000s	120.022us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	587.267us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	1.000s	93.178us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.000s	85.845us	1	1	100.00
		aes_csr_aliasing	4.000s	587.267us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	3.000s	70.627us	1	1	100.00
		aes_config_error	2.000s	130.955us	1	1	100.00
		aes_stress	3.000s	212.206us	1	1	100.00
V2	key_length	aes_smoke	3.000s	70.627us	1	1	100.00
		aes_config_error	2.000s	130.955us	1	1	100.00
		aes_stress	3.000s	212.206us	1	1	100.00
V2	back2back	aes_stress	3.000s	212.206us	1	1	100.00
		aes_b2b	12.000s	1.023ms	1	1	100.00
V2	backpressure	aes_stress	3.000s	212.206us	1	1	100.00
V2	multi_message	aes_smoke	3.000s	70.627us	1	1	100.00
		aes_config_error	2.000s	130.955us	1	1	100.00
		aes_stress	3.000s	212.206us	1	1	100.00
		aes_alert_reset	3.000s	188.200us	1	1	100.00
V2	failure_test	aes_man_cfg_err	2.000s	56.600us	1	1	100.00
		aes_config_error	2.000s	130.955us	1	1	100.00
		aes_alert_reset	3.000s	188.200us	1	1	100.00
V2	trigger_clear_test	aes_clear	3.000s	93.382us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	9.000s	1.286ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	3.000s	188.200us	1	1	100.00
V2	stress	aes_stress	3.000s	212.206us	1	1	100.00
V2	sideload	aes_stress	3.000s	212.206us	1	1	100.00
		aes_sideload	3.000s	127.224us	1	1	100.00
V2	deinitialization	aes_deinit	4.000s	449.319us	1	1	100.00
V2	stress_all	aes_stress_all	41.000s	2.415ms	1	1	100.00
V2	alert_test	aes_alert_test	2.000s	81.738us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	3.000s	82.502us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	3.000s	82.502us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	1.000s	61.884us	1	1	100.00
		aes_csr_rw	1.000s	85.845us	1	1	100.00
		aes_csr_aliasing	4.000s	587.267us	1	1	100.00
		aes_same_csr_outstanding	2.000s	57.529us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	1.000s	61.884us	1	1	100.00
		aes_csr_rw	1.000s	85.845us	1	1	100.00
		aes_csr_aliasing	4.000s	587.267us	1	1	100.00
		aes_same_csr_outstanding	2.000s	57.529us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	4.000s	96.865us	1	1	100.00
V2S	fault_inject	aes_fi	4.000s	151.358us	1	1	100.00
		aes_control_fi	2.000s	46.949us	1	1	100.00
		aes_cipher_fi	2.000s	55.717us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	2.000s	132.470us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	2.000s	132.470us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	2.000s	132.470us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	2.000s	132.470us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	2.000s	241.694us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	5.000s	534.925us	1	1	100.00
		aes_tl_intg_err	2.000s	174.973us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	2.000s	174.973us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	3.000s	188.200us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	2.000s	132.470us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	3.000s	70.627us	1	1	100.00
		aes_stress	3.000s	212.206us	1	1	100.00
		aes_alert_reset	3.000s	188.200us	1	1	100.00
		aes_core_fi	3.000s	116.460us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	2.000s	132.470us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	2.000s	55.486us	1	1	100.00
		aes_stress	3.000s	212.206us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	3.000s	212.206us	1	1	100.00
		aes_sideload	3.000s	127.224us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	2.000s	55.486us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	2.000s	55.486us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	2.000s	55.486us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	2.000s	55.486us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	2.000s	55.486us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	3.000s	212.206us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	3.000s	212.206us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	4.000s	151.358us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	4.000s	151.358us	1	1	100.00
		aes_control_fi	2.000s	46.949us	1	1	100.00
		aes_cipher_fi	2.000s	55.717us	1	1	100.00
		aes_ctr_fi	2.000s	145.098us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	4.000s	151.358us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	4.000s	151.358us	1	1	100.00
		aes_control_fi	2.000s	46.949us	1	1	100.00
		aes_cipher_fi	2.000s	55.717us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	2.000s	55.717us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	4.000s	151.358us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	4.000s	151.358us	1	1	100.00
		aes_control_fi	2.000s	46.949us	1	1	100.00
		aes_ctr_fi	2.000s	145.098us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	4.000s	151.358us	1	1	100.00
		aes_control_fi	2.000s	46.949us	1	1	100.00
		aes_cipher_fi	2.000s	55.717us	1	1	100.00
		aes_ctr_fi	2.000s	145.098us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	3.000s	188.200us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	4.000s	151.358us	1	1	100.00
		aes_control_fi	2.000s	46.949us	1	1	100.00
		aes_cipher_fi	2.000s	55.717us	1	1	100.00
		aes_ctr_fi	2.000s	145.098us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	4.000s	151.358us	1	1	100.00
		aes_control_fi	2.000s	46.949us	1	1	100.00
		aes_cipher_fi	2.000s	55.717us	1	1	100.00
		aes_ctr_fi	2.000s	145.098us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	4.000s	151.358us	1	1	100.00
		aes_control_fi	2.000s	46.949us	1	1	100.00
		aes_ctr_fi	2.000s	145.098us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	4.000s	151.358us	1	1	100.00
		aes_control_fi	2.000s	46.949us	1	1	100.00
		aes_cipher_fi	2.000s	55.717us	1	1	100.00
V2S		TOTAL			11	11	100.00
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	7.000s	1.505ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			31	32	96.88

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: aes_reg_block.status reset value: * has 1 failures:
  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.88557927148902814340219999053839085346219168550037673328463451974700282325876
      Line 159, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1505413330 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (64 [0x40] vs 0 [0x0]) Regname: aes_reg_block.status reset value: 0x0
        UVM_INFO @ 1505413330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---