EDN Simulation Results

Thursday September 25 2025 19:17:05 UTC

GitHub Revision: 8f374b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.870s 25.024us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.990s 17.500us 1 1 100.00
V1 csr_rw edn_csr_rw 0.750s 31.127us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.680s 181.220us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.120s 55.642us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.250s 36.570us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.750s 31.127us 1 1 100.00
edn_csr_aliasing 1.120s 55.642us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 0.950s 91.797us 1 1 100.00
V2 csrng_commands edn_genbits 0.950s 91.797us 1 1 100.00
V2 genbits edn_genbits 0.950s 91.797us 1 1 100.00
V2 interrupts edn_intr 0.820s 40.545us 1 1 100.00
V2 alerts edn_alert 1.040s 29.379us 1 1 100.00
V2 errs edn_err 0.780s 28.586us 1 1 100.00
V2 disable edn_disable 0.850s 22.324us 1 1 100.00
edn_disable_auto_req_mode 1.000s 50.113us 1 1 100.00
V2 stress_all edn_stress_all 4.180s 304.929us 1 1 100.00
V2 intr_test edn_intr_test 0.830s 46.662us 1 1 100.00
V2 alert_test edn_alert_test 0.940s 16.531us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.260s 44.548us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.260s 44.548us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.990s 17.500us 1 1 100.00
edn_csr_rw 0.750s 31.127us 1 1 100.00
edn_csr_aliasing 1.120s 55.642us 1 1 100.00
edn_same_csr_outstanding 1.320s 112.006us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.990s 17.500us 1 1 100.00
edn_csr_rw 0.750s 31.127us 1 1 100.00
edn_csr_aliasing 1.120s 55.642us 1 1 100.00
edn_same_csr_outstanding 1.320s 112.006us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 6.610s 1.079ms 1 1 100.00
edn_tl_intg_err 2.060s 93.303us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 0.960s 18.140us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.040s 29.379us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.610s 1.079ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.610s 1.079ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 6.610s 1.079ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.610s 1.079ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.040s 29.379us 1 1 100.00
edn_sec_cm 6.610s 1.079ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.040s 29.379us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.060s 93.303us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets