HMAC Simulation Results

Thursday September 25 2025 19:17:05 UTC

GitHub Revision: 8f374b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 5.170s 683.543us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.820s 20.452us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.880s 34.896us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.470s 4.394ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.260s 1.230ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.420s 64.524us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.880s 34.896us 1 1 100.00
hmac_csr_aliasing 4.260s 1.230ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 51.180s 5.990ms 1 1 100.00
V2 back_pressure hmac_back_pressure 22.810s 555.946us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.050s 701.154us 1 1 100.00
hmac_test_sha384_vectors 6.939m 12.647ms 1 1 100.00
hmac_test_sha512_vectors 19.640s 243.052us 1 1 100.00
hmac_test_hmac256_vectors 7.660s 280.850us 1 1 100.00
hmac_test_hmac384_vectors 9.700s 1.343ms 1 1 100.00
hmac_test_hmac512_vectors 10.190s 1.257ms 1 1 100.00
V2 burst_wr hmac_burst_wr 19.860s 4.181ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 1.290m 2.839ms 1 1 100.00
V2 error hmac_error 35.280s 33.357ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 49.110s 20.762ms 1 1 100.00
V2 save_and_restore hmac_smoke 5.170s 683.543us 1 1 100.00
hmac_long_msg 51.180s 5.990ms 1 1 100.00
hmac_back_pressure 22.810s 555.946us 1 1 100.00
hmac_datapath_stress 1.290m 2.839ms 1 1 100.00
hmac_burst_wr 19.860s 4.181ms 1 1 100.00
hmac_stress_all 4.416m 48.232ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 5.170s 683.543us 1 1 100.00
hmac_long_msg 51.180s 5.990ms 1 1 100.00
hmac_back_pressure 22.810s 555.946us 1 1 100.00
hmac_datapath_stress 1.290m 2.839ms 1 1 100.00
hmac_wipe_secret 49.110s 20.762ms 1 1 100.00
hmac_test_sha256_vectors 8.050s 701.154us 1 1 100.00
hmac_test_sha384_vectors 6.939m 12.647ms 1 1 100.00
hmac_test_sha512_vectors 19.640s 243.052us 1 1 100.00
hmac_test_hmac256_vectors 7.660s 280.850us 1 1 100.00
hmac_test_hmac384_vectors 9.700s 1.343ms 1 1 100.00
hmac_test_hmac512_vectors 10.190s 1.257ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 5.170s 683.543us 1 1 100.00
hmac_long_msg 51.180s 5.990ms 1 1 100.00
hmac_back_pressure 22.810s 555.946us 1 1 100.00
hmac_datapath_stress 1.290m 2.839ms 1 1 100.00
hmac_burst_wr 19.860s 4.181ms 1 1 100.00
hmac_error 35.280s 33.357ms 1 1 100.00
hmac_wipe_secret 49.110s 20.762ms 1 1 100.00
hmac_test_sha256_vectors 8.050s 701.154us 1 1 100.00
hmac_test_sha384_vectors 6.939m 12.647ms 1 1 100.00
hmac_test_sha512_vectors 19.640s 243.052us 1 1 100.00
hmac_test_hmac256_vectors 7.660s 280.850us 1 1 100.00
hmac_test_hmac384_vectors 9.700s 1.343ms 1 1 100.00
hmac_test_hmac512_vectors 10.190s 1.257ms 1 1 100.00
hmac_stress_all 4.416m 48.232ms 1 1 100.00
V2 stress_all hmac_stress_all 4.416m 48.232ms 1 1 100.00
V2 alert_test hmac_alert_test 0.620s 49.027us 1 1 100.00
V2 intr_test hmac_intr_test 0.760s 17.289us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.440s 63.544us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.440s 63.544us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.820s 20.452us 1 1 100.00
hmac_csr_rw 0.880s 34.896us 1 1 100.00
hmac_csr_aliasing 4.260s 1.230ms 1 1 100.00
hmac_same_csr_outstanding 2.030s 588.989us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.820s 20.452us 1 1 100.00
hmac_csr_rw 0.880s 34.896us 1 1 100.00
hmac_csr_aliasing 4.260s 1.230ms 1 1 100.00
hmac_same_csr_outstanding 2.030s 588.989us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.740s 39.461us 1 1 100.00
hmac_tl_intg_err 2.860s 417.192us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.860s 417.192us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 5.170s 683.543us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.250s 148.248us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 38.910s 4.501ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.390s 168.888us 1 1 100.00
TOTAL 28 28 100.00