I2C Simulation Results

Thursday September 25 2025 19:17:05 UTC

GitHub Revision: 8f374b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	41.740s	7.476ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	7.050s	3.432ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.720s	25.011us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.640s	56.409us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.160s	223.275us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.710s	433.267us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.880s	119.807us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.640s	56.409us	1	1	100.00
		i2c_csr_aliasing	1.710s	433.267us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.860s	14.836us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	1.887m	17.609ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	15.580s	6.637ms	1	1	100.00
V2	host_override	i2c_host_override	0.640s	45.652us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	46.120s	6.930ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.895m	2.435ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.240s	74.033us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.210s	165.502us	1	1	100.00
		i2c_host_fifo_reset_rx	6.270s	598.622us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	40.670s	7.160ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	29.890s	4.160ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.740s	10.385us	0	1	0.00
V2	target_glitch	i2c_target_glitch	3.280s	468.018us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	3.176m	39.320ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.060s	771.253us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	29.520s	975.512us	1	1	100.00
		i2c_target_intr_smoke	4.230s	2.695ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.670s	206.553us	1	1	100.00
		i2c_target_fifo_reset_tx	1.420s	212.279us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	2.016m	56.818ms	1	1	100.00
		i2c_target_stress_rd	29.520s	975.512us	1	1	100.00
		i2c_target_intr_stress_wr	5.270s	8.080ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.550s	23.743ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	2.570s	3.745ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.920s	6.204ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.920s	179.545us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.530s	214.019us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.610s	702.037us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	15.580s	6.637ms	1	1	100.00
		i2c_host_perf_precise	8.080s	1.114ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	29.890s	4.160ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.950s	362.413us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.070s	1.966ms	1	1	100.00
		i2c_target_nack_acqfull_addr	1.880s	1.174ms	1	1	100.00
		i2c_target_nack_txstretch	1.290s	305.199us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	7.980s	1.188ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.580s	527.403us	1	1	100.00
V2	alert_test	i2c_alert_test	0.610s	36.918us	1	1	100.00
V2	intr_test	i2c_intr_test	0.880s	43.210us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.230s	576.062us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.230s	576.062us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.720s	25.011us	1	1	100.00
		i2c_csr_rw	0.640s	56.409us	1	1	100.00
		i2c_csr_aliasing	1.710s	433.267us	1	1	100.00
		i2c_same_csr_outstanding	1.170s	270.925us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.720s	25.011us	1	1	100.00
		i2c_csr_rw	0.640s	56.409us	1	1	100.00
		i2c_csr_aliasing	1.710s	433.267us	1	1	100.00
		i2c_same_csr_outstanding	1.170s	270.925us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	1.320s	52.851us	1	1	100.00
		i2c_sec_cm	0.810s	220.804us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.320s	52.851us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	8.070s	187.910us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.560s	936.099us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	6.260s	692.408us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.102630875679573152163335110617509038414980373553971714457341821693048472186580
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  14835511 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  14835511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.32555647409985101466368522634199063794450138185109868448040423580099481165442
      Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @  10385212 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  10385212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.25692776347548868842752802560747451557000648189190681573936695095284849964692
      Line 90, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 187910237 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 187910237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.102675697121918179989498344249912453259514943616423838345681932785158247168006
      Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 692408437 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 692408437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.95397038431718674793077380488714287816697701096802076682862430777478145692328
      Line 142, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 17609360769 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @1238897
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.79799413609730281369071322426043135645137496610933173556061201553241505301645
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 468018295 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 468018295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.100528903647505489598923764721381650413963470642953743699529958184346225080211
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 936098570 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 936098570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---