KEYMGR Simulation Results

Thursday September 25 2025 19:17:05 UTC

GitHub Revision: 8f374b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.090s	172.571us	1	1	100.00
V1	random	keymgr_random	4.850s	173.646us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	0.950s	70.892us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	0.820s	14.870us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	5.480s	453.077us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	3.310s	727.234us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.330s	24.801us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	0.820s	14.870us	1	1	100.00
		keymgr_csr_aliasing	3.310s	727.234us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	4.710s	117.751us	1	1	100.00
V2	sideload	keymgr_sideload	10.900s	2.711ms	1	1	100.00
		keymgr_sideload_kmac	3.240s	793.679us	1	1	100.00
		keymgr_sideload_aes	1.840s	35.052us	1	1	100.00
		keymgr_sideload_otbn	2.390s	127.509us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	1.250s	70.494us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.710s	205.876us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.180s	258.813us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.050s	266.868us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	5.900s	3.921ms	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.750s	87.178us	1	1	100.00
V2	stress_all	keymgr_stress_all	13.090s	575.810us	0	1	0.00
V2	intr_test	keymgr_intr_test	0.680s	154.870us	1	1	100.00
V2	alert_test	keymgr_alert_test	0.840s	15.480us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	1.440s	170.616us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	1.440s	170.616us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	0.950s	70.892us	1	1	100.00
		keymgr_csr_rw	0.820s	14.870us	1	1	100.00
		keymgr_csr_aliasing	3.310s	727.234us	1	1	100.00
		keymgr_same_csr_outstanding	2.340s	235.283us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	0.950s	70.892us	1	1	100.00
		keymgr_csr_rw	0.820s	14.870us	1	1	100.00
		keymgr_csr_aliasing	3.310s	727.234us	1	1	100.00
		keymgr_same_csr_outstanding	2.340s	235.283us	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	8.650s	652.719us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	8.650s	652.719us	1	1	100.00
		keymgr_tl_intg_err	2.740s	137.592us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.530s	312.271us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.530s	312.271us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.530s	312.271us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.530s	312.271us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	11.210s	477.850us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	8.650s	652.719us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	8.650s	652.719us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	2.740s	137.592us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.530s	312.271us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	4.710s	117.751us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.850s	173.646us	1	1	100.00
		keymgr_csr_rw	0.820s	14.870us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.850s	173.646us	1	1	100.00
		keymgr_csr_rw	0.820s	14.870us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.850s	173.646us	1	1	100.00
		keymgr_csr_rw	0.820s	14.870us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.710s	205.876us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	5.900s	3.921ms	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	5.900s	3.921ms	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.850s	173.646us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.050s	440.544us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	8.650s	652.719us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	8.650s	652.719us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	8.650s	652.719us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.490s	231.628us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.710s	205.876us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	8.650s	652.719us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	8.650s	652.719us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	8.650s	652.719us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.490s	231.628us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.490s	231.628us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	8.650s	652.719us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.490s	231.628us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	8.650s	652.719us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.490s	231.628us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	10.740s	3.507ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			28	30	93.33

Failure Buckets

• UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:

  • Test keymgr_stress_all has 1 failures.

    • 0.keymgr_stress_all.83767394560955484995309943090476047636565762928903275548731452766964989967966
      Line 1386, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 575810030 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_0
        UVM_INFO @ 575810030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.109459713810220551929003866757379031892516703683411178368744676628798282473271
      Line 1379, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3506909327 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3506909327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---