KMAC/MASKED Simulation Results

Thursday September 25 2025 19:17:05 UTC

GitHub Revision: 8f374b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	6.040s	464.055us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.870s	44.985us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.940s	70.271us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.680s	1.131ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.830s	257.364us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.340s	549.837us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.940s	70.271us	1	1	100.00
		kmac_csr_aliasing	3.830s	257.364us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.890s	40.164us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.310s	121.299us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	30.179m	96.409ms	1	1	100.00
V2	burst_write	kmac_burst_write	3.606m	5.324ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	28.650s	2.474ms	1	1	100.00
		kmac_test_vectors_sha3_256	24.687m	69.376ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.000s	3.593ms	1	1	100.00
		kmac_test_vectors_sha3_512	17.543m	45.995ms	1	1	100.00
		kmac_test_vectors_shake_128	2.012m	6.555ms	1	1	100.00
		kmac_test_vectors_shake_256	4.579m	45.980ms	1	1	100.00
		kmac_test_vectors_kmac	2.420s	57.079us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.700s	90.424us	1	1	100.00
V2	sideload	kmac_sideload	1.187m	1.238ms	1	1	100.00
V2	app	kmac_app	4.106m	13.076ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.420m	64.253ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	32.220s	7.145ms	1	1	100.00
V2	error	kmac_error	1.500m	5.591ms	1	1	100.00
V2	key_error	kmac_key_error	7.220s	1.311ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.600s	553.571us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	28.030s	4.143ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.010s	90.733us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	4.590s	437.719us	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.400s	23.960us	1	1	100.00
V2	stress_all	kmac_stress_all	14.958m	139.503ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.800s	42.983us	1	1	100.00
V2	alert_test	kmac_alert_test	1.210s	77.747us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.490s	51.110us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.490s	51.110us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.870s	44.985us	1	1	100.00
		kmac_csr_rw	0.940s	70.271us	1	1	100.00
		kmac_csr_aliasing	3.830s	257.364us	1	1	100.00
		kmac_same_csr_outstanding	2.150s	128.517us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.870s	44.985us	1	1	100.00
		kmac_csr_rw	0.940s	70.271us	1	1	100.00
		kmac_csr_aliasing	3.830s	257.364us	1	1	100.00
		kmac_same_csr_outstanding	2.150s	128.517us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.660s	46.582us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.660s	46.582us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.660s	46.582us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.660s	46.582us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.720s	128.091us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.389m	10.284ms	1	1	100.00
		kmac_tl_intg_err	3.810s	242.943us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.810s	242.943us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.400s	23.960us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	6.040s	464.055us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.187m	1.238ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.660s	46.582us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.389m	10.284ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.389m	10.284ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.389m	10.284ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	6.040s	464.055us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.400s	23.960us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.389m	10.284ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.454m	12.008ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	6.040s	464.055us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	44.390s	1.994ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.50502281616120153625963340276327381638300411247462509761147749497744472374694
      Line 203, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1994393194 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 1994393194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---