KMAC/UNMASKED Simulation Results

Thursday September 25 2025 19:17:05 UTC

GitHub Revision: 8f374b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	3.700s	305.609us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.100s	46.925us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.960s	21.704us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.340s	299.230us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.640s	1.314ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.180s	141.077us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.960s	21.704us	1	1	100.00
		kmac_csr_aliasing	6.640s	1.314ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.660s	29.188us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.290s	45.534us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	30.209m	168.083ms	1	1	100.00
V2	burst_write	kmac_burst_write	7.522m	27.601ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	30.800s	8.935ms	1	1	100.00
		kmac_test_vectors_sha3_256	26.970s	1.382ms	1	1	100.00
		kmac_test_vectors_sha3_384	21.693m	67.947ms	1	1	100.00
		kmac_test_vectors_sha3_512	12.504m	95.122ms	1	1	100.00
		kmac_test_vectors_shake_128	2.207m	8.925ms	1	1	100.00
		kmac_test_vectors_shake_256	1.567m	6.456ms	1	1	100.00
		kmac_test_vectors_kmac	2.670s	146.906us	1	1	100.00
		kmac_test_vectors_kmac_xof	1.860s	182.960us	1	1	100.00
V2	sideload	kmac_sideload	1.744m	6.895ms	1	1	100.00
V2	app	kmac_app	2.664m	72.088ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.788m	6.126ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.922m	9.437ms	1	1	100.00
V2	error	kmac_error	18.740s	691.672us	1	1	100.00
V2	key_error	kmac_key_error	2.730s	592.104us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	17.710s	10.045ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	22.150s	1.134ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	7.900s	212.989us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	48.960s	7.678ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.200s	44.754us	1	1	100.00
V2	stress_all	kmac_stress_all	5.728m	15.508ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.730s	29.767us	1	1	100.00
V2	alert_test	kmac_alert_test	0.930s	32.319us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.880s	253.802us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.880s	253.802us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.100s	46.925us	1	1	100.00
		kmac_csr_rw	0.960s	21.704us	1	1	100.00
		kmac_csr_aliasing	6.640s	1.314ms	1	1	100.00
		kmac_same_csr_outstanding	1.510s	120.960us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.100s	46.925us	1	1	100.00
		kmac_csr_rw	0.960s	21.704us	1	1	100.00
		kmac_csr_aliasing	6.640s	1.314ms	1	1	100.00
		kmac_same_csr_outstanding	1.510s	120.960us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.030s	85.929us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.030s	85.929us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.030s	85.929us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.030s	85.929us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.130s	362.670us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	41.800s	12.461ms	1	1	100.00
		kmac_tl_intg_err	1.920s	307.339us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.920s	307.339us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.200s	44.754us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	3.700s	305.609us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.744m	6.895ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.030s	85.929us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	41.800s	12.461ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	41.800s	12.461ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	41.800s	12.461ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	3.700s	305.609us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.200s	44.754us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	41.800s	12.461ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.162m	200.000ms	0	1	0.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	3.700s	305.609us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	58.820s	35.034ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.58341026838181627356882593334287855295055633964469337970169243946400829554938
      Line 75, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10045462810 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4fc2a000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
        UVM_INFO @ 10045462810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test kmac_mubi has 1 failures.

    • 0.kmac_mubi.32586094723696798509401826011641049098227392702130814323035609233489171077677
      Line 228, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_mubi/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---