PATTGEN Simulation Results

Thursday September 25 2025 19:17:05 UTC

GitHub Revision: 8f374b4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	1.000s	92.893us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	1.000s	34.334us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	1.000s	16.322us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	2.000s	749.517us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	1.000s	368.980us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	1.000s	32.219us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.000s	16.322us	1	1	100.00
		pattgen_csr_aliasing	1.000s	368.980us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	2.267m	93.055ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	10.000s	5.505ms	1	1	100.00
V2	error	pattgen_error	2.000s	23.863us	1	1	100.00
V2	stress_all	pattgen_stress_all			0	1	0.00
V2	alert_test	pattgen_alert_test	2.000s	12.725us	1	1	100.00
V2	intr_test	pattgen_intr_test	1.000s	22.828us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.000s	40.399us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.000s	40.399us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	1.000s	34.334us	1	1	100.00
		pattgen_csr_rw	1.000s	16.322us	1	1	100.00
		pattgen_csr_aliasing	1.000s	368.980us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	49.424us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	1.000s	34.334us	1	1	100.00
		pattgen_csr_rw	1.000s	16.322us	1	1	100.00
		pattgen_csr_aliasing	1.000s	368.980us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	49.424us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	2.000s	220.239us	1	1	100.00
		pattgen_sec_cm	2.000s	93.856us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	2.000s	220.239us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	19.000s	11.755ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	3.000s	379.577us	1	1	100.00
		TOTAL			16	18	88.89

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.24359102817340845073251433386452218117939933984166199623463417493364108079778
      Line 114, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2943509840 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 2943535099 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 2943535099 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 1/5
        UVM_INFO @ 2943630337 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
      

• Job timed out after * minutes has 1 failures:

  • Test pattgen_stress_all has 1 failures.

    • 0.pattgen_stress_all.22580679271955562568730546506709649176670584719910825228221205016588800883321
      Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log

        Job timed out after 180 minutes