ROM_CTRL/32KB Simulation Results

Thursday September 25 2025 19:17:05 UTC

GitHub Revision: 8f374b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.090s 235.460us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 4.830s 304.713us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 3.730s 126.556us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5.620s 173.520us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 3.370s 790.118us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 3.950s 241.068us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 3.730s 126.556us 1 1 100.00
rom_ctrl_csr_aliasing 3.370s 790.118us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.520s 138.419us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 3.570s 454.122us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.500s 309.208us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 11.700s 1.625ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 6.990s 261.863us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 3.590s 125.552us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 6.680s 164.070us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 6.680s 164.070us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 4.830s 304.713us 1 1 100.00
rom_ctrl_csr_rw 3.730s 126.556us 1 1 100.00
rom_ctrl_csr_aliasing 3.370s 790.118us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.670s 557.558us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 4.830s 304.713us 1 1 100.00
rom_ctrl_csr_rw 3.730s 126.556us 1 1 100.00
rom_ctrl_csr_aliasing 3.370s 790.118us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.670s 557.558us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 45.790s 5.179ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 14.960s 1.102ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.332m 1.284ms 1 1 100.00
rom_ctrl_tl_intg_err 24.960s 220.231us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.332m 1.284ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 3.332m 1.284ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 45.790s 5.179ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 45.790s 5.179ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 45.790s 5.179ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 45.790s 5.179ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 45.790s 5.179ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.332m 1.284ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.332m 1.284ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.090s 235.460us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.090s 235.460us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.090s 235.460us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 24.960s 220.231us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 45.790s 5.179ms 1 1 100.00
rom_ctrl_kmac_err_chk 6.990s 261.863us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 45.790s 5.179ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 45.790s 5.179ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 45.790s 5.179ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 14.960s 1.102ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.332m 1.284ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.299m 2.901ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00