SPI_DEVICE/1R1W Simulation Results

Thursday September 25 2025 19:17:05 UTC

GitHub Revision: 8f374b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	32.280s	20.157ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.990s	46.791us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.070s	300.070us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	16.500s	355.757us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.190s	114.271us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.990s	103.331us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.070s	300.070us	1	1	100.00
		spi_device_csr_aliasing	5.190s	114.271us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.850s	20.826us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.870s	59.023us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.960s	53.202us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.730s	2.939us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.710s	6.407us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.980s	473.338us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.980s	473.338us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	8.450s	3.898ms	1	1	100.00
		spi_device_tpm_sts_read	0.790s	124.721us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	18.640s	5.328ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.830s	31.614us	1	1	100.00
		spi_device_flash_all	40.650s	3.505ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.300s	729.688us	1	1	100.00
		spi_device_flash_all	40.650s	3.505ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.300s	729.688us	1	1	100.00
		spi_device_flash_all	40.650s	3.505ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	40.650s	3.505ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	10.730s	3.317ms	1	1	100.00
		spi_device_flash_all	40.650s	3.505ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	10.730s	3.317ms	1	1	100.00
		spi_device_flash_all	40.650s	3.505ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	10.730s	3.317ms	1	1	100.00
		spi_device_flash_all	40.650s	3.505ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	10.730s	3.317ms	1	1	100.00
		spi_device_flash_all	40.650s	3.505ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	10.730s	3.317ms	1	1	100.00
		spi_device_flash_all	40.650s	3.505ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	3.410s	2.913ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	2.760s	353.993us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.760s	353.993us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.760s	353.993us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	2.260s	518.934us	1	1	100.00
		spi_device_read_buffer_direct	9.130s	1.455ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.760s	353.993us	1	1	100.00
		spi_device_flash_all	40.650s	3.505ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	40.650s	3.505ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	40.650s	3.505ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.750s	156.858us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.750s	156.858us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	32.280s	20.157ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	4.310s	684.974us	1	1	100.00
V2	stress_all	spi_device_stress_all	20.660s	3.362ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.070s	49.215us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.020s	40.579us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.990s	172.494us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.990s	172.494us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.990s	46.791us	1	1	100.00
		spi_device_csr_rw	1.070s	300.070us	1	1	100.00
		spi_device_csr_aliasing	5.190s	114.271us	1	1	100.00
		spi_device_same_csr_outstanding	2.310s	133.218us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.990s	46.791us	1	1	100.00
		spi_device_csr_rw	1.070s	300.070us	1	1	100.00
		spi_device_csr_aliasing	5.190s	114.271us	1	1	100.00
		spi_device_same_csr_outstanding	2.310s	133.218us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.070s	70.447us	1	1	100.00
		spi_device_tl_intg_err	5.310s	110.918us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	5.310s	110.918us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	58.740s	17.033ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.57697382444791061199990675617159163444992842568289757050117406225010618971958
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2020940 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[99])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2020940 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2020940 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[995])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.107989709296619072921923099209099003560587723194324818786419757710379298542677
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3655514 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x875e44 [100001110101111001000100] vs 0x0 [0])
        UVM_ERROR @   3718514 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x91c002 [100100011100000000000010] vs 0x0 [0])
        UVM_ERROR @   3791514 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x47e5a [1000111111001011010] vs 0x0 [0])
        UVM_ERROR @   3848514 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x86a5cc [100001101010010111001100] vs 0x0 [0])
        UVM_ERROR @   3860514 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x85c576 [100001011100010101110110] vs 0x0 [0])