SPI_DEVICE/2P Simulation Results

Thursday September 25 2025 19:17:05 UTC

GitHub Revision: 8f374b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 4.169m 225.318ms 1 1 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.230s 153.170us 1 1 100.00
V1 csr_rw spi_device_csr_rw 1.440s 70.535us 1 1 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 8.860s 193.052us 1 1 100.00
V1 csr_aliasing spi_device_csr_aliasing 15.020s 2.329ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 2.660s 178.697us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 1.440s 70.535us 1 1 100.00
spi_device_csr_aliasing 15.020s 2.329ms 1 1 100.00
V1 mem_walk spi_device_mem_walk 0.910s 12.870us 1 1 100.00
V1 mem_partial_access spi_device_mem_partial_access 1.710s 172.239us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 csb_read spi_device_csb_read 0.870s 19.281us 1 1 100.00
V2 mem_parity spi_device_mem_parity 1.080s 17.435us 1 1 100.00
V2 mem_cfg spi_device_ram_cfg 0.710s 16.212us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 2.160s 362.251us 1 1 100.00
V2 tpm_write spi_device_tpm_rw 2.160s 362.251us 1 1 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 1.150s 75.640us 1 1 100.00
spi_device_tpm_sts_read 0.980s 96.500us 1 1 100.00
V2 tpm_fully_random_case spi_device_tpm_all 9.780s 977.472us 1 1 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 5.800s 3.201ms 1 1 100.00
spi_device_flash_all 1.015m 71.732ms 1 1 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 5.720s 1.668ms 1 1 100.00
spi_device_flash_all 1.015m 71.732ms 1 1 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 5.720s 1.668ms 1 1 100.00
spi_device_flash_all 1.015m 71.732ms 1 1 100.00
V2 cmd_info_slots spi_device_flash_all 1.015m 71.732ms 1 1 100.00
V2 cmd_read_status spi_device_intercept 11.060s 6.144ms 1 1 100.00
spi_device_flash_all 1.015m 71.732ms 1 1 100.00
V2 cmd_read_jedec spi_device_intercept 11.060s 6.144ms 1 1 100.00
spi_device_flash_all 1.015m 71.732ms 1 1 100.00
V2 cmd_read_sfdp spi_device_intercept 11.060s 6.144ms 1 1 100.00
spi_device_flash_all 1.015m 71.732ms 1 1 100.00
V2 cmd_fast_read spi_device_intercept 11.060s 6.144ms 1 1 100.00
spi_device_flash_all 1.015m 71.732ms 1 1 100.00
V2 cmd_read_pipeline spi_device_intercept 11.060s 6.144ms 1 1 100.00
spi_device_flash_all 1.015m 71.732ms 1 1 100.00
V2 flash_cmd_upload spi_device_upload 3.040s 704.232us 1 1 100.00
V2 mailbox_command spi_device_mailbox 2.980s 511.045us 1 1 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 2.980s 511.045us 1 1 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 2.980s 511.045us 1 1 100.00
V2 cmd_read_buffer spi_device_flash_mode 20.930s 1.787ms 1 1 100.00
spi_device_read_buffer_direct 5.710s 729.650us 1 1 100.00
V2 cmd_dummy_cycle spi_device_mailbox 2.980s 511.045us 1 1 100.00
spi_device_flash_all 1.015m 71.732ms 1 1 100.00
V2 quad_spi spi_device_flash_all 1.015m 71.732ms 1 1 100.00
V2 dual_spi spi_device_flash_all 1.015m 71.732ms 1 1 100.00
V2 4b_3b_feature spi_device_cfg_cmd 1.820s 34.485us 1 1 100.00
V2 write_enable_disable spi_device_cfg_cmd 1.820s 34.485us 1 1 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 4.169m 225.318ms 1 1 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 1.314m 53.842ms 1 1 100.00
V2 stress_all spi_device_stress_all 1.110s 62.833us 1 1 100.00
V2 alert_test spi_device_alert_test 0.740s 41.511us 1 1 100.00
V2 intr_test spi_device_intr_test 1.000s 41.161us 1 1 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 1.680s 96.334us 1 1 100.00
V2 tl_d_illegal_access spi_device_tl_errors 1.680s 96.334us 1 1 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.230s 153.170us 1 1 100.00
spi_device_csr_rw 1.440s 70.535us 1 1 100.00
spi_device_csr_aliasing 15.020s 2.329ms 1 1 100.00
spi_device_same_csr_outstanding 2.860s 61.596us 1 1 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.230s 153.170us 1 1 100.00
spi_device_csr_rw 1.440s 70.535us 1 1 100.00
spi_device_csr_aliasing 15.020s 2.329ms 1 1 100.00
spi_device_same_csr_outstanding 2.860s 61.596us 1 1 100.00
V2 TOTAL 22 22 100.00
V2S tl_intg_err spi_device_sec_cm 1.160s 75.738us 1 1 100.00
spi_device_tl_intg_err 5.170s 111.401us 1 1 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 5.170s 111.401us 1 1 100.00
V2S TOTAL 2 2 100.00
Unmapped tests spi_device_flash_mode_ignore_cmds 35.920s 18.694ms 1 1 100.00
TOTAL 33 33 100.00