SPI_HOST Simulation Results

Thursday September 25 2025 19:17:05 UTC

GitHub Revision: 8f374b4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	15.000s	1.750ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.000s	78.009us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	30.734us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	2.000s	288.761us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	109.347us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	1.000s	84.072us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	30.734us	1	1	100.00
		spi_host_csr_aliasing	2.000s	109.347us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	15.906us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	22.352us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	1.000s	72.552us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.000s	130.190us	1	1	100.00
		spi_host_error_cmd	2.000s	48.602us	1	1	100.00
		spi_host_event	24.000s	1.774ms	1	1	100.00
V2	clock_rate	spi_host_speed	3.000s	83.339us	1	1	100.00
V2	speed	spi_host_speed	3.000s	83.339us	1	1	100.00
V2	chip_select_timing	spi_host_speed	3.000s	83.339us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	5.000s	164.268us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	20.553us	1	1	100.00
V2	cpol_cpha	spi_host_speed	3.000s	83.339us	1	1	100.00
V2	full_cycle	spi_host_speed	3.000s	83.339us	1	1	100.00
V2	duplex	spi_host_smoke	15.000s	1.750ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	15.000s	1.750ms	1	1	100.00
V2	stress_all	spi_host_stress_all	37.000s	2.449ms	1	1	100.00
V2	spien	spi_host_spien	5.000s	1.015ms	1	1	100.00
V2	stall	spi_host_status_stall	24.000s	724.780us	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	3.000s	471.706us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	3.000s	130.190us	1	1	100.00
V2	alert_test	spi_host_alert_test	2.000s	54.416us	1	1	100.00
V2	intr_test	spi_host_intr_test	1.000s	39.577us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	1.000s	444.504us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	1.000s	444.504us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.000s	78.009us	1	1	100.00
		spi_host_csr_rw	2.000s	30.734us	1	1	100.00
		spi_host_csr_aliasing	2.000s	109.347us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	19.761us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.000s	78.009us	1	1	100.00
		spi_host_csr_rw	2.000s	30.734us	1	1	100.00
		spi_host_csr_aliasing	2.000s	109.347us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	19.761us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	1.000s	927.705us	1	1	100.00
		spi_host_sec_cm	2.000s	131.573us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	1.000s	927.705us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	2.417m	15.464ms	1	1	100.00
		TOTAL			26	26	100.00