SRAM_CTRL/MAIN Simulation Results

Thursday September 25 2025 19:17:05 UTC

GitHub Revision: 8f374b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	20.690s	2.061ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.700s	17.741us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.670s	39.151us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.540s	270.991us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.790s	141.904us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.860s	1.857ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.670s	39.151us	1	1	100.00
		sram_ctrl_csr_aliasing	0.790s	141.904us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.943m	7.278ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.015m	5.253ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	12.274m	22.062ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.269m	4.099ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	26.782m	496.689ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.550m	22.476ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	35.990s	27.654ms	1	1	100.00
V2	executable	sram_ctrl_executable	6.996m	17.285ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	14.120s	15.342ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.708m	46.650ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	41.230s	800.005us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	16.900s	752.503us	1	1	100.00
		sram_ctrl_throughput_w_readback	26.460s	845.045us	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.406m	27.452ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.730s	1.246ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	1.384h	1.005s	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.980s	54.774us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.880s	442.779us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.880s	442.779us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.700s	17.741us	1	1	100.00
		sram_ctrl_csr_rw	0.670s	39.151us	1	1	100.00
		sram_ctrl_csr_aliasing	0.790s	141.904us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.710s	51.791us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.700s	17.741us	1	1	100.00
		sram_ctrl_csr_rw	0.670s	39.151us	1	1	100.00
		sram_ctrl_csr_aliasing	0.790s	141.904us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.710s	51.791us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	23.000s	3.782ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.950s	1.814us	0	1	0.00
		sram_ctrl_tl_intg_err	2.250s	280.305us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.950s	1.814us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.250s	280.305us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.406m	27.452ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.406m	27.452ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.670s	39.151us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	6.996m	17.285ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	6.996m	17.285ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	6.996m	17.285ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	35.990s	27.654ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	6.960s	1.729ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	23.000s	3.782ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	8.190s	1.356ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	20.690s	2.061ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	20.690s	2.061ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	6.996m	17.285ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.950s	1.814us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	35.990s	27.654ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.950s	1.814us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.950s	1.814us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	20.690s	2.061ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.950s	1.814us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.084m	1.006ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.50885949456982809369775489307246575062210022448619196571651874450559969709018
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   1813627 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   1813627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---