SRAM_CTRL/RET Simulation Results

Thursday September 25 2025 19:17:05 UTC

GitHub Revision: 8f374b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.380s	64.513us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.670s	13.899us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.740s	12.545us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.160s	48.897us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.820s	11.953us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.110s	55.055us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.740s	12.545us	1	1	100.00
		sram_ctrl_csr_aliasing	0.820s	11.953us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.980s	1.350ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.610s	119.107us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	55.830s	3.421ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.009m	8.804ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	15.290s	1.808ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	9.413m	15.901ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.320s	4.489ms	1	1	100.00
V2	executable	sram_ctrl_executable	6.139m	10.945ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	5.580s	424.029us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.419m	9.004ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.090s	179.080us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	1.370s	41.745us	1	1	100.00
		sram_ctrl_throughput_w_readback	2.170s	211.414us	1	1	100.00
V2	regwen	sram_ctrl_regwen	9.036m	29.894ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.090s	49.097us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	28.057m	20.243ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.630s	13.913us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.480s	41.171us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.480s	41.171us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.670s	13.899us	1	1	100.00
		sram_ctrl_csr_rw	0.740s	12.545us	1	1	100.00
		sram_ctrl_csr_aliasing	0.820s	11.953us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.770s	56.590us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.670s	13.899us	1	1	100.00
		sram_ctrl_csr_rw	0.740s	12.545us	1	1	100.00
		sram_ctrl_csr_aliasing	0.820s	11.953us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.770s	56.590us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.680s	421.002us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.770s	1.862us	0	1	0.00
		sram_ctrl_tl_intg_err	1.780s	141.317us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.770s	1.862us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.780s	141.317us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	9.036m	29.894ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	9.036m	29.894ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.740s	12.545us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	6.139m	10.945ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	6.139m	10.945ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	6.139m	10.945ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.320s	4.489ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.910s	91.455us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.680s	421.002us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.000s	61.895us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.380s	64.513us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.380s	64.513us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	6.139m	10.945ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.770s	1.862us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.320s	4.489ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.770s	1.862us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.770s	1.862us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.380s	64.513us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.770s	1.862us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	29.770s	2.501ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.37782351280893913216262985692594362779956884758075245827282337200629915213544
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  91455235 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  91455235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.42285381488101786262825896843033496939941773814250527345921987892262600807505
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   1862339 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   1862339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---