SYSRST_CTRL Simulation Results

Thursday September 25 2025 19:17:05 UTC

GitHub Revision: `8f374b4`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	1.570s	2.135ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	4.980s	2.440ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	4.690s	2.395ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	4.420s	2.280ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	7.950s	4.030ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	2.230s	2.083ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	48.600s	34.806ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	7.250s	2.570ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	1.540s	2.135ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	2.230s	2.083ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	7.250s	2.570ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	3.388m	116.524ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	1.444m	44.485ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	2.000s	3.094ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	5.000s	5.957ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	4.950s	2.511ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	1.610s	2.170ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	6.570s	3.247ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	1.090s	2.694ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	4.350s	3.726ms	0	1	0.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.072m	32.580ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	4.490s	8.886ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	2.470s	2.019ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	2.520s	2.022ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	3.260s	2.255ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	3.260s	2.255ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	7.950s	4.030ms	1	1	100.00
		sysrst_ctrl_csr_rw	2.230s	2.083ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	7.250s	2.570ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	12.290s	7.177ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	7.950s	4.030ms	1	1	100.00
		sysrst_ctrl_csr_rw	2.230s	2.083ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	7.250s	2.570ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	12.290s	7.177ms	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	sysrst_ctrl_sec_cm	44.010s	22.013ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	38.170s	42.831ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	38.170s	42.831ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	7.700s	7.302ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 1 failures:

Test sysrst_ctrl_ultra_low_pwr has 1 failures.

0.sysrst_ctrl_ultra_low_pwr.22967034482829883373698479278794453174994651075385048288685181268435222171820
Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2318650551 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 3726150551 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 3726150551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---