UART Simulation Results

Thursday September 25 2025 19:17:05 UTC

GitHub Revision: 8f374b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	5.580s	5.548ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.660s	15.478us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.730s	80.737us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.130s	407.383us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.870s	21.935us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.610s	87.487us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.730s	80.737us	1	1	100.00
		uart_csr_aliasing	0.870s	21.935us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	16.950s	52.033ms	1	1	100.00
V2	parity	uart_smoke	5.580s	5.548ms	1	1	100.00
		uart_tx_rx	16.950s	52.033ms	1	1	100.00
V2	parity_error	uart_intr	8.230s	12.880ms	1	1	100.00
		uart_rx_parity_err	32.550s	51.838ms	1	1	100.00
V2	watermark	uart_tx_rx	16.950s	52.033ms	1	1	100.00
		uart_intr	8.230s	12.880ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.625m	145.851ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	36.260s	67.079ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	13.450s	36.637ms	1	1	100.00
V2	rx_frame_err	uart_intr	8.230s	12.880ms	1	1	100.00
V2	rx_break_err	uart_intr	8.230s	12.880ms	1	1	100.00
V2	rx_timeout	uart_intr	8.230s	12.880ms	1	1	100.00
V2	perf	uart_perf	6.854m	10.759ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.050s	822.067us	1	1	100.00
V2	line_loopback	uart_loopback	2.050s	822.067us	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	4.060s	6.149ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	4.770s	3.491ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.730s	446.116us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	2.550s	1.382ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	7.441m	83.630ms	1	1	100.00
V2	stress_all	uart_stress_all	12.375m	22.775ms	0	1	0.00
V2	alert_test	uart_alert_test	0.790s	38.201us	1	1	100.00
V2	intr_test	uart_intr_test	0.590s	48.420us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.100s	122.018us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.100s	122.018us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.660s	15.478us	1	1	100.00
		uart_csr_rw	0.730s	80.737us	1	1	100.00
		uart_csr_aliasing	0.870s	21.935us	1	1	100.00
		uart_same_csr_outstanding	1.130s	124.222us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.660s	15.478us	1	1	100.00
		uart_csr_rw	0.730s	80.737us	1	1	100.00
		uart_csr_aliasing	0.870s	21.935us	1	1	100.00
		uart_same_csr_outstanding	1.130s	124.222us	1	1	100.00
V2		TOTAL			16	18	88.89
V2S	tl_intg_err	uart_sec_cm	1.280s	167.396us	1	1	100.00
		uart_tl_intg_err	1.320s	943.111us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.320s	943.111us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	3.640s	729.604us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.10111249641834969121044874522541348347143456726419816809688801069656815113253
      Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 2123683783 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 2123683783 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 2123683783 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 2346378763 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2,                                 clk_pulses: 0
        UVM_ERROR @ 2346455687 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (130 [0x82] vs 127 [0x7f]) reg name: uart_reg_block.rdata
      

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:

  • Test uart_stress_all has 1 failures.

    • 0.uart_stress_all.29082078487619423446860757649531913127504448991246921824213645973705201511895
      Line 92, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        UVM_ERROR @ 19231065459 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 19231065459 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 20058855459 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 3
        UVM_ERROR @ 20058865459 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 20058875459 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 43 [0x2b]) reg name: uart_reg_block.rdata