CHIP Simulation Results

Thursday September 25 2025 19:17:05 UTC

GitHub Revision: `8f374b4`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.710m	3.354ms	1	1	100.00
		chip_sw_example_rom	1.185m	2.381ms	1	1	100.00
		chip_sw_example_manufacturer	2.583m	2.925ms	1	1	100.00
		chip_sw_example_concurrency	1.897m	3.178ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.191m	5.785ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.337m	3.921ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	37.981m	31.748ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	56.249m	26.792ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	6.063m	6.593ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	56.249m	26.792ms	1	1	100.00
		chip_csr_rw	3.337m	3.921ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.980s	206.027us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.505m	4.053ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.505m	4.053ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.505m	4.053ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	7.315m	4.558ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	7.315m	4.558ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.609m	4.354ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.806m	4.427ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.752m	3.575ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	6.896m	4.395ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	28.278m	13.093ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	5.228m	5.121ms	1	1	100.00
V1		TOTAL			18	18	100.00
V2	chip_pin_mux	chip_padctrl_attributes	3.515m	5.338ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.515m	5.338ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.219m	3.156ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.407m	2.944ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.005m	3.295ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	15.431m	12.862ms	1	1	100.00
		chip_tap_straps_testunlock0	3.148m	4.200ms	1	1	100.00
		chip_tap_straps_rma	3.851m	4.914ms	1	1	100.00
		chip_tap_straps_prod	1.814m	2.225ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.769m	3.309ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	13.334m	9.637ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	7.975m	6.513ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	7.975m	6.513ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.019m	6.698ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	45.567m	27.710ms	1	1	100.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.334m	3.729ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.898m	5.837ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	57.125m	18.820ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.859m	2.681ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	12.141m	6.917ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.717m	2.956ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.808m	7.687ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.530m	2.328ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.545m	5.008ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.863m	2.605ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.974m	3.008ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	10.588m	7.537ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.675m	5.206ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.836m	2.781ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.675m	5.206ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.873m	3.427ms	1	1	100.00
		chip_sw_aes_smoketest	3.557m	2.561ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.761m	2.484ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.638m	3.048ms	1	1	100.00
		chip_sw_csrng_smoketest	2.752m	3.198ms	1	1	100.00
		chip_sw_entropy_src_smoketest	15.947m	7.710ms	1	1	100.00
		chip_sw_gpio_smoketest	3.235m	2.779ms	1	1	100.00
		chip_sw_hmac_smoketest	2.817m	2.601ms	1	1	100.00
		chip_sw_kmac_smoketest	3.200m	3.113ms	1	1	100.00
		chip_sw_otbn_smoketest	14.271m	8.113ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.855m	5.884ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.656m	5.000ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.141m	2.702ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.599m	3.348ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.544m	2.354ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.115m	3.333ms	1	1	100.00
		chip_sw_uart_smoketest	2.490m	3.231ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.328m	3.092ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.837m	4.569ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.284h	62.354ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	42.156m	14.762ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	3.237m	5.113ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.931m	3.508ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.829m	3.417ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.981h	53.842ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.035h	57.313ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	55.750s	2.370ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	55.750s	2.370ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	56.249m	26.792ms	1	1	100.00
		chip_same_csr_outstanding	21.033m	15.459ms	1	1	100.00
		chip_csr_hw_reset	3.191m	5.785ms	1	1	100.00
		chip_csr_rw	3.337m	3.921ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	56.249m	26.792ms	1	1	100.00
		chip_same_csr_outstanding	21.033m	15.459ms	1	1	100.00
		chip_csr_hw_reset	3.191m	5.785ms	1	1	100.00
		chip_csr_rw	3.337m	3.921ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	4.640s	39.996us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.830s	49.567us	1	1	100.00
		xbar_smoke_large_delays	56.020s	9.486ms	1	1	100.00
		xbar_smoke_slow_rsp	49.250s	5.679ms	1	1	100.00
		xbar_random_zero_delays	4.560s	37.233us	1	1	100.00
		xbar_random_large_delays	24.200s	3.782ms	1	1	100.00
		xbar_random_slow_rsp	1.124m	7.943ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	17.050s	216.693us	1	1	100.00
		xbar_error_and_unmapped_addr	12.620s	198.872us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	57.030s	2.699ms	1	1	100.00
		xbar_error_and_unmapped_addr	12.620s	198.872us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	15.830s	318.390us	1	1	100.00
		xbar_access_same_device_slow_rsp	2.446m	16.748ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	17.180s	327.549us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	3.200m	3.682ms	1	1	100.00
		xbar_stress_all_with_error	51.060s	845.027us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	11.599m	25.196ms	1	1	100.00
		xbar_stress_all_with_reset_error	1.643m	722.973us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	42.156m	14.762ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	36.935m	27.573ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	42.196m	14.867ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	34.769m	11.461ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	43.877m	15.546ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	44.178m	16.488ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	43.491m	15.659ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	41.819m	14.956ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	19.810s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	18.250s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	19.630s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	16.070s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	20.070s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	22.380s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	26.430s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	20.340s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	18.710s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	16.710s	10.140us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	17.800s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	18.390s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	16.720s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	16.730s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	17.450s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	17.110s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	16.750s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	17.070s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	16.860s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	18.700s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	17.790s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.710s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	17.520s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.760s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.600s	10.400us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	33.464m	11.991ms	1	1	100.00
		rom_e2e_asm_init_dev	41.266m	16.212ms	1	1	100.00
		rom_e2e_asm_init_prod	43.047m	15.751ms	1	1	100.00
		rom_e2e_asm_init_prod_end	42.651m	17.138ms	1	1	100.00
		rom_e2e_asm_init_rma	40.814m	15.975ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	41.209m	15.096ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	40.108m	15.110ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	40.612m	15.287ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	43.665m	19.701ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	54.275m	34.289ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	54.275m	34.289ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	1.909m	2.733ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.859m	2.681ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	1.515m	2.276ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.629m	2.854ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	11.634m	6.855ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.406m	2.951ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.322m	4.802ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.968m	5.662ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.077m	5.122ms	1	1	100.00
		chip_plic_all_irqs_10	4.015m	3.390ms	1	1	100.00
		chip_plic_all_irqs_20	6.440m	4.685ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.743m	3.613ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	17.000m	11.542ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.146m	3.612ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.918m	2.379ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	17.126m	8.426ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	18.796m	8.917ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	11.898m	7.865ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.062h	254.963ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.171m	4.178ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.855m	5.884ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.171m	4.178ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.033m	10.378ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.033m	10.378ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.889m	7.125ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	7.031m	5.421ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.162m	5.637ms	1	1	100.00
		chip_sw_aes_idle	2.629m	2.854ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.574m	2.751ms	1	1	100.00
		chip_sw_kmac_idle	1.703m	2.614ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.559m	4.639ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.424m	3.101ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.652m	4.875ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.058m	4.985ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	15.353m	10.482ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.682m	4.831ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	7.274m	5.070ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.194m	4.154ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.050m	5.231ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.922m	4.297ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.214m	4.873ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.019m	6.698ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	10.226m	11.522ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.194m	4.154ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.050m	5.231ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.334m	3.729ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.898m	5.837ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	57.125m	18.820ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.859m	2.681ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	12.141m	6.917ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.717m	2.956ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.808m	7.687ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.530m	2.328ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.545m	5.008ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.863m	2.605ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.047m	2.831ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.884m	5.333ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.105m	6.829ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	50.980m	24.913ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.024m	2.558ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.507m	3.437ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	19.502m	11.267ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.688m	2.935ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	6.229m	5.048ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	20.202m	21.414ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	26.615m	14.452ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.019m	6.698ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.159m	3.766ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.866m	3.402ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.968m	5.662ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	17.126m	8.426ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.465m	5.765ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	5.201m	4.529ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.959m	5.858ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.548m	3.428ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.242h	27.160ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.849m	2.743ms	1	1	100.00
		chip_sw_edn_entropy_reqs	10.122m	5.673ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.849m	2.743ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.465m	5.765ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.630m	2.620ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	17.906m	24.153ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	10.389m	4.955ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.898m	5.837ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.720m	4.688ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.334m	3.729ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.076h	44.264ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	17.906m	24.153ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.020m	3.799ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	24.424m	11.951ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.208m	4.210ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.076h	44.264ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.208m	4.210ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.208m	4.210ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.208m	4.210ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.208m	4.210ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.968m	5.662ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	4.039m	10.857ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	9.906m	4.956ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	7.548m	5.253ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	7.548m	5.253ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.215m	3.309ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.717m	2.956ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.574m	2.751ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.430m	3.298ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.102m	3.668ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.544m	5.115ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.681m	5.061ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.135m	4.602ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.731m	3.837ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	24.424m	11.951ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.808m	7.687ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	17.132m	9.092ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	11.634m	6.855ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	36.635m	11.733ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.585m	2.580ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.943m	2.655ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.530m	2.328ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	24.424m	11.951ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	5.931m	5.999ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.378m	2.355ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	8.475m	5.192ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.703m	2.614ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.322m	4.802ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	15.431m	12.862ms	1	1	100.00
		chip_tap_straps_rma	3.851m	4.914ms	1	1	100.00
		chip_tap_straps_prod	1.814m	2.225ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.537m	3.115ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	5.931m	5.999ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	5.931m	5.999ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	5.931m	5.999ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	19.728m	8.840ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.208m	4.210ms	1	1	100.00
		chip_sw_flash_rma_unlocked	1.076h	44.264ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.403m	2.929ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.987m	6.964ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.938m	7.169ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.570m	6.103ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.931m	5.999ms	1	1	100.00
		chip_sw_keymgr_key_derivation	24.424m	11.951ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.905m	9.009ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	8.924m	8.982ms	1	1	100.00
		chip_prim_tl_access	4.039m	10.857ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	10.226m	11.522ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.682m	4.831ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	7.274m	5.070ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.194m	4.154ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.050m	5.231ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.922m	4.297ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.214m	4.873ms	1	1	100.00
		chip_tap_straps_dev	15.431m	12.862ms	1	1	100.00
		chip_tap_straps_rma	3.851m	4.914ms	1	1	100.00
		chip_tap_straps_prod	1.814m	2.225ms	1	1	100.00
		chip_rv_dm_lc_disabled	6.725m	13.869ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.331m	3.943ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.406m	3.948ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.286m	3.194ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.328m	3.531ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	20.301m	31.701ms	1	1	100.00
		chip_rv_dm_lc_disabled	6.725m	13.869ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.082h	46.353ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.006h	47.472ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	10.210m	11.076ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.018h	48.052ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	20.301m	31.701ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.076m	2.512ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.079m	2.613ms	1	1	100.00
		rom_volatile_raw_unlock	1.063m	2.367ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	55.657m	16.856ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	57.125m	18.820ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.162m	5.637ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.162m	5.637ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.162m	5.637ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	5.480m	3.551ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	5.931m	5.999ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	17.906m	24.153ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.480m	3.551ms	1	1	100.00
		chip_sw_keymgr_key_derivation	24.424m	11.951ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.094m	4.887ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.575m	2.540ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	17.906m	24.153ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.480m	3.551ms	1	1	100.00
		chip_sw_keymgr_key_derivation	24.424m	11.951ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.094m	4.887ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.575m	2.540ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	5.931m	5.999ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.966m	5.157ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.537m	3.115ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.403m	2.929ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.987m	6.964ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.938m	7.169ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.570m	6.103ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.931m	5.999ms	1	1	100.00
		chip_prim_tl_access	4.039m	10.857ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.039m	10.857ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	18.557m	8.638ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	3.386m	6.238ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	15.717m	22.820ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.488m	7.164ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.053m	6.750ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	7.381m	6.107ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	11.554m	21.581ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	12.516m	15.844ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	9.033m	10.378ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	15.898m	10.838ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	6.037m	5.438ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	3.386m	6.238ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.112m	3.549ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	32.974m	33.209ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.998m	7.596ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	5.139m	5.719ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	29.489m	25.112ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	12.146m	8.610ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	17.357m	10.389ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	21.402m	26.354ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.839m	3.375ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.968m	5.662ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.905m	9.009ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.905m	9.009ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	17.357m	10.389ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	29.489m	25.112ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	6.037m	5.438ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.855m	5.884ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.709m	3.587ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.585m	3.341ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.670m	3.760ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	17.000m	11.542ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.750m	3.150ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.968m	5.662ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	18.796m	8.917ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.310m	4.559ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.833m	4.857ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.631m	2.829ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	1.575m	2.540ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.585m	3.341ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.585m	3.341ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	14.111m	11.637ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	13.614m	14.043ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.709m	3.587ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.173m	4.415ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	6.349m	7.083ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.851m	4.914ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.725m	13.869ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.077m	5.122ms	1	1	100.00
		chip_plic_all_irqs_10	4.015m	3.390ms	1	1	100.00
		chip_plic_all_irqs_20	6.440m	4.685ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.609m	2.971ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.253m	2.867ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	42.156m	14.762ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.939m	6.850ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.839m	3.567ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.447m	3.553ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.175m	3.171ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.094m	4.887ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.545m	5.008ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	7.020m	7.224ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.752m	8.042ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	8.924m	8.982ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.968m	5.662ms	1	1	100.00
		chip_sw_data_integrity_escalation	7.975m	6.513ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	12.146m	8.610ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	20.067m	22.139ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.241m	2.738ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.628m	3.739ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.231m	4.110ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	20.067m	22.139ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	20.067m	22.139ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	40.859m	20.208ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	40.859m	20.208ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.228m	6.099ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	54.275m	34.289ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.617m	3.365ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.349m	2.805ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.688m	4.024ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.002m	3.360ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	18.365m	8.170ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.485h	31.248ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	30.611m	12.377ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	1.714m	2.715ms	1	1	100.00
V2		TOTAL			240	275	87.27
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.618m	2.601ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.427m	3.176ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.592h	72.814ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	15.313m	5.750ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	8.976m	13.836ms	0	1	0.00
		rom_e2e_jtag_debug_dev	18.284m	11.003ms	1	1	100.00
		rom_e2e_jtag_debug_rma	21.055m	12.273ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.171m	3.673ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.948m	3.874ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.706m	3.861ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.012s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.507m	4.373ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	5.311m	2.852ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	19.864m	7.759ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	17.123m	7.510ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.358m	2.251ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.325m	5.221ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.572m	2.804ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	7.085m	5.553ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.727m	5.770ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.494m	4.647ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	17.357m	10.389ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	8.976m	13.836ms	0	1	0.00
		rom_e2e_jtag_debug_dev	18.284m	11.003ms	1	1	100.00
		rom_e2e_jtag_debug_rma	21.055m	12.273ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.510m	5.666ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.968m	5.662ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.469h	38.539ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.469h	38.539ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.382m	3.267ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	7.315m	4.558ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	54.914m	18.353ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.305m	2.929ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.951m	5.225ms	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	31.742m	31.764ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.277m	3.247ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.930m	3.506ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	2.922m	3.347ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	13.871s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.315m	2.722ms	1	1	100.00
		TOTAL			287	326	88.04

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.70473148551166616214416005647978212237193343855829089177719215896123014485030
    Line 499, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.35097680013921135858143924333653824438116813257483591513856337984143793921284
    Line 512, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.93272833720346953008599857543467590059324313684580381920484529405197359746764
    Line 538, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.81450438191708315171381515967687148431409064532437056743039626233591630728835
    Line 532, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.88629611124108322664402766134774635154390950609188932539369957156014230528339
    Line 524, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.48885978251772180642769990591812241875849629103232043143609183427504600308434
    Line 485, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.14708747646582519051297610165183464895551294079517481283535842553908052149775
    Line 494, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.46914221087326284229721929051653925236675315702150516712675355264665535201908
    Line 498, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.39471962485311993467491583480624807512352747834235798112488114102705781119994
    Line 494, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.95909092559680346776747582555230342186577484448568792241503330478799368888471
    Line 490, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.104133434595260911122552445461419946710260701509812531585209129833370845160181
    Line 500, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.17541648915383129819003546513935614644116114115509135459309712521666933976495
    Line 505, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.91316613411458667605170326365409006643647339800121009824788138630312869951403
    Line 515, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.84866617802547532111417316731378531792979583509437758764069544802859704971894
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.175s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.37752293315929789328159734181243756044450477061636840298412832154389906009972
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.216s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.81892109985654711369548115087117476908824417125798573399409158387240519582288
    Line 567, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.75454864824568900953226800022319185806885677583724038914754438414826012439332
    Line 574, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.13347997208175386954220105521780533532085570808907812610342321201207858386806
    Line 548, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.102850042321812252657006642526120160671095327473869357343425316910576024179274
    Line 505, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.6745436451161033688603482399439838508771706991265133532418043666786521414538
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3567.233986 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3567.233986 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.33094842022082324756232071470986468363905811472672155383821546600106282444793
    Line 411, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 31764.217281 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 31764.217281 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@83940) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.20155965290141393083378364902458829805621107491389702071377997386990728102255
Line 412, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3341.396556 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@83940) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3341.396556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.60847644619833169322506597616713801827464129083623339665974413018770501528266
    Line 409, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34288.762821 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34288.762821 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.114231853363011215982435934904343746089536649700976565591970414768504439615655
    Line 401, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2951.222920 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 43!
  UVM_INFO @ 2951.222920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.4573564860473516959115034369485870606958843721838455946616852071986211655217
    Line 393, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2378.802884 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2378.802884 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.100954718769536773403002600288454671798704400171831940240357968924405958880191
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.103333771873441922933227365290796695705975814992726786555420925812349909061024
    Line 392, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 3298.010880 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 3298.010880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33206) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.19630341867040519255374293230971029034553830567248646252609922223870374235023
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2370.186858 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33206) { a_addr: 'h1070c  a_data: 'hcceb595e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h15  a_opcode: 'h4  a_user: 'h18192  d_param: 'h0  d_source: 'h15  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2370.186858 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.17166986761233303611965695020419293355755632265172388907512560364409442440965
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3508.451500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3508.451500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.9994179075469315792402673464238737730802469767303085539583912991475548640274
    Line 404, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3416.500000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3416.500000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.58510096807720813928326795787945345926057794834407798392067310792917273228490
    Line 546, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.70190482953906233273597643911510731575023791087402403941636185355360032483423
    Line 539, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 1 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.37088858208126943281491728756188676422211725339624848272432733352975732170484
    Line 427, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 13835.586628 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 13835.586628 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```