ADC_CTRL Simulation Results

Monday September 29 2025 18:33:12 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	11.270s	5.949ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.020s	1.099ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.000s	510.516us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	10.580s	54.524ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.100s	1.086ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.190s	347.511us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.000s	510.516us	1	1	100.00
		adc_ctrl_csr_aliasing	2.100s	1.086ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	12.521m	498.331ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	9.663m	324.536ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	4.818m	167.242ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	2.015m	484.806ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	2.519m	173.405ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	8.030m	589.905ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	14.566m	553.712ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	15.284m	541.116ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	3.110s	5.172ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	51.960s	30.640ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	13.370s	79.654ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	13.490m	495.833ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	0.750s	353.937us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	0.780s	359.245us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	1.780s	380.715us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	1.780s	380.715us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.020s	1.099ms	1	1	100.00
		adc_ctrl_csr_rw	1.000s	510.516us	1	1	100.00
		adc_ctrl_csr_aliasing	2.100s	1.086ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.860s	2.436ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.020s	1.099ms	1	1	100.00
		adc_ctrl_csr_rw	1.000s	510.516us	1	1	100.00
		adc_ctrl_csr_aliasing	2.100s	1.086ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.860s	2.436ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	2.840s	4.405ms	1	1	100.00
		adc_ctrl_tl_intg_err	14.240s	8.502ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	14.240s	8.502ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	6.460s	2.097ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00