AES/UNMASKED Simulation Results

Monday September 29 2025 18:33:12 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	70.329us	1	1	100.00
V1	smoke	aes_smoke	2.000s	73.557us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	67.331us	1	1	100.00
V1	csr_rw	aes_csr_rw	2.000s	90.395us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	4.000s	2.133ms	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	2.000s	73.395us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	69.369us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	2.000s	90.395us	1	1	100.00
		aes_csr_aliasing	2.000s	73.395us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	2.000s	73.557us	1	1	100.00
		aes_config_error	4.000s	146.862us	1	1	100.00
		aes_stress	2.000s	143.502us	1	1	100.00
V2	key_length	aes_smoke	2.000s	73.557us	1	1	100.00
		aes_config_error	4.000s	146.862us	1	1	100.00
		aes_stress	2.000s	143.502us	1	1	100.00
V2	back2back	aes_stress	2.000s	143.502us	1	1	100.00
		aes_b2b	5.000s	123.895us	1	1	100.00
V2	backpressure	aes_stress	2.000s	143.502us	1	1	100.00
V2	multi_message	aes_smoke	2.000s	73.557us	1	1	100.00
		aes_config_error	4.000s	146.862us	1	1	100.00
		aes_stress	2.000s	143.502us	1	1	100.00
		aes_alert_reset	2.000s	78.652us	1	1	100.00
V2	failure_test	aes_man_cfg_err	2.000s	105.645us	1	1	100.00
		aes_config_error	4.000s	146.862us	1	1	100.00
		aes_alert_reset	2.000s	78.652us	1	1	100.00
V2	trigger_clear_test	aes_clear	4.000s	373.644us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	3.000s	203.752us	1	1	100.00
V2	reset_recovery	aes_alert_reset	2.000s	78.652us	1	1	100.00
V2	stress	aes_stress	2.000s	143.502us	1	1	100.00
V2	sideload	aes_stress	2.000s	143.502us	1	1	100.00
		aes_sideload	2.000s	112.666us	1	1	100.00
V2	deinitialization	aes_deinit	2.000s	65.575us	1	1	100.00
V2	stress_all	aes_stress_all	22.000s	16.165ms	1	1	100.00
V2	alert_test	aes_alert_test	1.000s	65.132us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	2.000s	103.917us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	2.000s	103.917us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	67.331us	1	1	100.00
		aes_csr_rw	2.000s	90.395us	1	1	100.00
		aes_csr_aliasing	2.000s	73.395us	1	1	100.00
		aes_same_csr_outstanding	2.000s	238.367us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	67.331us	1	1	100.00
		aes_csr_rw	2.000s	90.395us	1	1	100.00
		aes_csr_aliasing	2.000s	73.395us	1	1	100.00
		aes_same_csr_outstanding	2.000s	238.367us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	3.000s	101.119us	1	1	100.00
V2S	fault_inject	aes_fi	2.000s	195.587us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	2.000s	53.205us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	1.000s	224.049us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	1.000s	224.049us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	1.000s	224.049us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	1.000s	224.049us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	2.000s	291.364us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	4.000s	3.681ms	1	1	100.00
		aes_tl_intg_err	2.000s	244.980us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	2.000s	244.980us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	2.000s	78.652us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	1.000s	224.049us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	2.000s	73.557us	1	1	100.00
		aes_stress	2.000s	143.502us	1	1	100.00
		aes_alert_reset	2.000s	78.652us	1	1	100.00
		aes_core_fi	2.000s	463.500us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	1.000s	224.049us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	2.000s	110.523us	1	1	100.00
		aes_stress	2.000s	143.502us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	2.000s	143.502us	1	1	100.00
		aes_sideload	2.000s	112.666us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	2.000s	110.523us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	2.000s	110.523us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	2.000s	110.523us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	2.000s	110.523us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	2.000s	110.523us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	2.000s	143.502us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	2.000s	143.502us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	2.000s	195.587us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	2.000s	195.587us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	2.000s	53.205us	1	1	100.00
		aes_ctr_fi	2.000s	123.276us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	2.000s	195.587us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	2.000s	195.587us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	2.000s	53.205us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	2.000s	53.205us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	2.000s	195.587us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	2.000s	195.587us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_ctr_fi	2.000s	123.276us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	2.000s	195.587us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	2.000s	53.205us	1	1	100.00
		aes_ctr_fi	2.000s	123.276us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	2.000s	78.652us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	2.000s	195.587us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	2.000s	53.205us	1	1	100.00
		aes_ctr_fi	2.000s	123.276us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	2.000s	195.587us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	2.000s	53.205us	1	1	100.00
		aes_ctr_fi	2.000s	123.276us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	2.000s	195.587us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_ctr_fi	2.000s	123.276us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	2.000s	195.587us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	2.000s	53.205us	1	1	100.00
V2S		TOTAL			10	11	90.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	6.000s	290.636us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			30	32	93.75

Failure Buckets

• Job timed out after * minutes has 1 failures:

  • Test aes_control_fi has 1 failures.

    • 0.aes_control_fi.24030711763184616650347474018883106330046953622912071525875953979060963384807
      Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_control_fi/latest/run.log

        Job timed out after 1 minutes
      

• UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.72510065329116785680058965107825120914621683031494240880173758140814772320258
      Line 410, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 290636323 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @ 290636323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---