EDN Simulation Results

Monday September 29 2025 18:33:12 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.020s	28.713us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.800s	36.892us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.820s	24.120us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.330s	251.184us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.030s	22.141us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	0.860s	166.380us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.820s	24.120us	1	1	100.00
		edn_csr_aliasing	1.030s	22.141us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.180s	60.423us	1	1	100.00
V2	csrng_commands	edn_genbits	1.180s	60.423us	1	1	100.00
V2	genbits	edn_genbits	1.180s	60.423us	1	1	100.00
V2	interrupts	edn_intr	0.950s	24.932us	1	1	100.00
V2	alerts	edn_alert	1.050s	40.518us	1	1	100.00
V2	errs	edn_err	1.070s	21.869us	1	1	100.00
V2	disable	edn_disable	0.830s	18.098us	1	1	100.00
		edn_disable_auto_req_mode	1.070s	40.248us	1	1	100.00
V2	stress_all	edn_stress_all	2.060s	294.957us	1	1	100.00
V2	intr_test	edn_intr_test	0.890s	18.295us	1	1	100.00
V2	alert_test	edn_alert_test	0.850s	25.528us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	1.480s	674.810us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	1.480s	674.810us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.800s	36.892us	1	1	100.00
		edn_csr_rw	0.820s	24.120us	1	1	100.00
		edn_csr_aliasing	1.030s	22.141us	1	1	100.00
		edn_same_csr_outstanding	1.080s	229.292us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.800s	36.892us	1	1	100.00
		edn_csr_rw	0.820s	24.120us	1	1	100.00
		edn_csr_aliasing	1.030s	22.141us	1	1	100.00
		edn_same_csr_outstanding	1.080s	229.292us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	6.610s	2.079ms	1	1	100.00
		edn_tl_intg_err	1.460s	116.527us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.900s	48.013us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.050s	40.518us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.610s	2.079ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.610s	2.079ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	6.610s	2.079ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.610s	2.079ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.050s	40.518us	1	1	100.00
		edn_sec_cm	6.610s	2.079ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.050s	40.518us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.460s	116.527us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	28.640s	3.240ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00