HMAC Simulation Results

Monday September 29 2025 18:33:12 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 1.880s 143.297us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.800s 39.207us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.940s 42.657us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 3.850s 116.038us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 2.610s 394.166us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 45.180s 22.709ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.940s 42.657us 1 1 100.00
hmac_csr_aliasing 2.610s 394.166us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 13.710s 3.075ms 1 1 100.00
V2 back_pressure hmac_back_pressure 49.080s 4.718ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.138m 22.960ms 1 1 100.00
hmac_test_sha384_vectors 20.560s 1.153ms 1 1 100.00
hmac_test_sha512_vectors 6.011m 10.338ms 1 1 100.00
hmac_test_hmac256_vectors 7.660s 241.543us 1 1 100.00
hmac_test_hmac384_vectors 9.520s 2.698ms 1 1 100.00
hmac_test_hmac512_vectors 8.620s 2.482ms 1 1 100.00
V2 burst_wr hmac_burst_wr 5.950s 517.363us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 15.536m 26.182ms 1 1 100.00
V2 error hmac_error 49.380s 5.067ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 19.630s 1.999ms 1 1 100.00
V2 save_and_restore hmac_smoke 1.880s 143.297us 1 1 100.00
hmac_long_msg 13.710s 3.075ms 1 1 100.00
hmac_back_pressure 49.080s 4.718ms 1 1 100.00
hmac_datapath_stress 15.536m 26.182ms 1 1 100.00
hmac_burst_wr 5.950s 517.363us 1 1 100.00
hmac_stress_all 18.790s 615.767us 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 1.880s 143.297us 1 1 100.00
hmac_long_msg 13.710s 3.075ms 1 1 100.00
hmac_back_pressure 49.080s 4.718ms 1 1 100.00
hmac_datapath_stress 15.536m 26.182ms 1 1 100.00
hmac_wipe_secret 19.630s 1.999ms 1 1 100.00
hmac_test_sha256_vectors 3.138m 22.960ms 1 1 100.00
hmac_test_sha384_vectors 20.560s 1.153ms 1 1 100.00
hmac_test_sha512_vectors 6.011m 10.338ms 1 1 100.00
hmac_test_hmac256_vectors 7.660s 241.543us 1 1 100.00
hmac_test_hmac384_vectors 9.520s 2.698ms 1 1 100.00
hmac_test_hmac512_vectors 8.620s 2.482ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 1.880s 143.297us 1 1 100.00
hmac_long_msg 13.710s 3.075ms 1 1 100.00
hmac_back_pressure 49.080s 4.718ms 1 1 100.00
hmac_datapath_stress 15.536m 26.182ms 1 1 100.00
hmac_burst_wr 5.950s 517.363us 1 1 100.00
hmac_error 49.380s 5.067ms 1 1 100.00
hmac_wipe_secret 19.630s 1.999ms 1 1 100.00
hmac_test_sha256_vectors 3.138m 22.960ms 1 1 100.00
hmac_test_sha384_vectors 20.560s 1.153ms 1 1 100.00
hmac_test_sha512_vectors 6.011m 10.338ms 1 1 100.00
hmac_test_hmac256_vectors 7.660s 241.543us 1 1 100.00
hmac_test_hmac384_vectors 9.520s 2.698ms 1 1 100.00
hmac_test_hmac512_vectors 8.620s 2.482ms 1 1 100.00
hmac_stress_all 18.790s 615.767us 1 1 100.00
V2 stress_all hmac_stress_all 18.790s 615.767us 1 1 100.00
V2 alert_test hmac_alert_test 0.620s 40.572us 1 1 100.00
V2 intr_test hmac_intr_test 0.780s 38.432us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.740s 503.894us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.740s 503.894us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.800s 39.207us 1 1 100.00
hmac_csr_rw 0.940s 42.657us 1 1 100.00
hmac_csr_aliasing 2.610s 394.166us 1 1 100.00
hmac_same_csr_outstanding 1.980s 376.844us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.800s 39.207us 1 1 100.00
hmac_csr_rw 0.940s 42.657us 1 1 100.00
hmac_csr_aliasing 2.610s 394.166us 1 1 100.00
hmac_same_csr_outstanding 1.980s 376.844us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.420s 458.434us 1 1 100.00
hmac_tl_intg_err 3.250s 927.347us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.250s 927.347us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 1.880s 143.297us 1 1 100.00
V3 stress_reset hmac_stress_reset 1.030s 153.055us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 52.450s 1.283ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.290s 96.521us 1 1 100.00
TOTAL 28 28 100.00