I2C Simulation Results

Monday September 29 2025 18:33:12 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	14.030s	2.704ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	5.780s	882.721us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.800s	20.418us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.850s	70.905us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.420s	235.126us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.310s	59.719us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.030s	36.063us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.850s	70.905us	1	1	100.00
		i2c_csr_aliasing	1.310s	59.719us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.760s	13.465us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	6.166m	43.745ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	27.480s	3.052ms	1	1	100.00
V2	host_override	i2c_host_override	0.950s	29.537us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	44.430s	3.188ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	38.310s	8.958ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.870s	480.106us	1	1	100.00
		i2c_host_fifo_fmt_empty	7.050s	1.048ms	1	1	100.00
		i2c_host_fifo_reset_rx	4.310s	300.502us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.739m	11.746ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	21.030s	828.072us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.380s	150.680us	0	1	0.00
V2	target_glitch	i2c_target_glitch	2.050s	475.531us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	5.787m	29.970ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.300s	2.682ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	5.390s	451.489us	1	1	100.00
		i2c_target_intr_smoke	5.200s	2.790ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.110s	400.557us	1	1	100.00
		i2c_target_fifo_reset_tx	1.350s	470.418us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	21.680s	23.114ms	1	1	100.00
		i2c_target_stress_rd	5.390s	451.489us	1	1	100.00
		i2c_target_intr_stress_wr	1.205m	14.245ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.350s	1.227ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	5.070s	10.037ms	0	1	0.00
V2	bad_address	i2c_target_bad_addr	3.130s	2.955ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.680s	1.101ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.220s	1.042ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	0.900s	2.707us	0	1	0.00
V2	host_mode_config_perf	i2c_host_perf	27.480s	3.052ms	1	1	100.00
		i2c_host_perf_precise	4.270s	494.177us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	21.030s	828.072us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	5.220s	478.518us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.290s	592.628us	1	1	100.00
		i2c_target_nack_acqfull_addr	1.860s	1.026ms	1	1	100.00
		i2c_target_nack_txstretch	1.360s	217.305us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.390s	1.759ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.550s	463.095us	1	1	100.00
V2	alert_test	i2c_alert_test	0.630s	45.844us	1	1	100.00
V2	intr_test	i2c_intr_test	0.730s	37.184us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.820s	437.334us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.820s	437.334us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.800s	20.418us	1	1	100.00
		i2c_csr_rw	0.850s	70.905us	1	1	100.00
		i2c_csr_aliasing	1.310s	59.719us	1	1	100.00
		i2c_same_csr_outstanding	0.900s	19.638us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.800s	20.418us	1	1	100.00
		i2c_csr_rw	0.850s	70.905us	1	1	100.00
		i2c_csr_aliasing	1.310s	59.719us	1	1	100.00
		i2c_same_csr_outstanding	0.900s	19.638us	1	1	100.00
V2		TOTAL			32	38	84.21
V2S	tl_intg_err	i2c_tl_intg_err	1.960s	877.525us	1	1	100.00
		i2c_sec_cm	0.840s	154.818us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.960s	877.525us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	9.660s	269.160us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	0.770s	71.080us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	14.470s	1.068ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			41	50	82.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.39267511619967590487088536030706184856804401820220220649372319623759093563554
      Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 269159821 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 269159821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.53544260922367957694876060866685960361568409001247130518811245345317208242605
      Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1068387721 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1068387721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.44372629398118874147297166736054988888420970267493298089052234476232671445781
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  13464666 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  13464666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.27767967606646026459779259113678785979789057804512449372092035841997994620324
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 475531039 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 475531039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 1 failures:

  • Test i2c_target_stretch has 1 failures.

    • 0.i2c_target_stretch.74600710105296395376994818661334476347015959405432428249449014300723017290980
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log

        UVM_FATAL @ 10037031553 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
        UVM_INFO @ 10037031553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.32331014449275531074207828401197757768194513952192796372750481382313029628826
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @  71080195 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 192 [0xc0])
        UVM_INFO @  71080195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.61622084669718267005480113377824062712543494058727891680387617861473218910312
      Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 150680257 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @9264
      

• Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:

  • Test i2c_target_fifo_watermarks_tx has 1 failures.

    • 0.i2c_target_fifo_watermarks_tx.112679152183294271176363400380769919646095334104462903555029795046384789085783
      Line 118, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_fifo_watermarks_tx/latest/run.log

        Error-[CNST-CIF] Constraints inconsistency failure
        src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
          Constraints are inconsistent and cannot be solved.
          Please check the inconsistent constraints being printed above and rewrite
          them.
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.88500443981543877472848918550360629794541918648138146419432745055014592994458
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 217305215 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 217305215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---