KMAC/MASKED Simulation Results

Monday September 29 2025 18:33:12 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	25.880s	30.480ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.860s	23.189us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.830s	43.236us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	5.570s	334.172us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.710s	1.827ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.760s	51.379us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.830s	43.236us	1	1	100.00
		kmac_csr_aliasing	6.710s	1.827ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.890s	22.422us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.150s	83.279us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	35.234m	90.047ms	1	1	100.00
V2	burst_write	kmac_burst_write	3.694m	7.575ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	32.380s	9.549ms	1	1	100.00
		kmac_test_vectors_sha3_256	29.472m	114.121ms	1	1	100.00
		kmac_test_vectors_sha3_384	22.390s	1.571ms	1	1	100.00
		kmac_test_vectors_sha3_512	14.380s	8.700ms	1	1	100.00
		kmac_test_vectors_shake_128	2.642m	35.913ms	1	1	100.00
		kmac_test_vectors_shake_256	4.793m	11.178ms	1	1	100.00
		kmac_test_vectors_kmac	3.220s	195.397us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.310s	69.116us	1	1	100.00
V2	sideload	kmac_sideload	27.910s	2.442ms	1	1	100.00
V2	app	kmac_app	16.880s	4.430ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	57.070s	2.224ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.151m	38.915ms	1	1	100.00
V2	error	kmac_error	6.469m	20.645ms	1	1	100.00
V2	key_error	kmac_key_error	4.420s	929.155us	0	1	0.00
V2	sideload_invalid	kmac_sideload_invalid	2.220s	39.110us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	25.410s	1.669ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.250s	65.718us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	49.240s	78.413ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.260s	48.777us	1	1	100.00
V2	stress_all	kmac_stress_all	1.424m	9.580ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.040s	54.627us	1	1	100.00
V2	alert_test	kmac_alert_test	1.140s	36.606us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.730s	57.864us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.730s	57.864us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.860s	23.189us	1	1	100.00
		kmac_csr_rw	0.830s	43.236us	1	1	100.00
		kmac_csr_aliasing	6.710s	1.827ms	1	1	100.00
		kmac_same_csr_outstanding	2.140s	341.196us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.860s	23.189us	1	1	100.00
		kmac_csr_rw	0.830s	43.236us	1	1	100.00
		kmac_csr_aliasing	6.710s	1.827ms	1	1	100.00
		kmac_same_csr_outstanding	2.140s	341.196us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.610s	118.759us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.610s	118.759us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.610s	118.759us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.610s	118.759us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.610s	818.989us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.334m	9.693ms	1	1	100.00
		kmac_tl_intg_err	3.250s	139.481us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.250s	139.481us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.260s	48.777us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	25.880s	30.480ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	27.910s	2.442ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.610s	118.759us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.334m	9.693ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.334m	9.693ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.334m	9.693ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	25.880s	30.480ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.260s	48.777us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.334m	9.693ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.810s	529.696us	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	25.880s	30.480ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.316m	15.227ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
  • Test kmac_key_error has 1 failures.

    • 0.kmac_key_error.76098217114290973998998667756699311809255129532179695254502049052266033337517
      Line 90, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_key_error/latest/run.log

        UVM_ERROR @ 929155063 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
        UVM_INFO @ 929155063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---