| V1 |
smoke |
kmac_smoke |
22.190s |
520.945us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
1.130s |
30.885us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
0.800s |
81.070us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
7.000s |
671.379us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
3.660s |
200.992us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
2.260s |
70.354us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
0.800s |
81.070us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.660s |
200.992us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
0.820s |
36.454us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
1.490s |
92.513us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
3.897m |
41.356ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
9.373m |
8.878ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
21.189m |
17.705ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
29.660s |
6.626ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
16.160s |
433.180us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
14.210m |
95.712ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
2.409m |
38.347ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
18.527m |
115.669ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
2.240s |
35.084us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
2.020s |
65.679us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
4.162m |
12.083ms |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
3.704m |
58.874ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
2.357m |
41.512ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
1.240m |
12.249ms |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
1.373m |
16.672ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
5.210s |
12.599ms |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
3.140s |
141.696us |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
11.660s |
2.480ms |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
18.630s |
642.827us |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
8.260s |
1.151ms |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
1.190s |
43.315us |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
42.130s |
12.495ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
0.940s |
93.368us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
1.060s |
32.903us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
3.540s |
1.143ms |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
3.540s |
1.143ms |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
1.130s |
30.885us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
0.800s |
81.070us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.660s |
200.992us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.950s |
90.059us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
1.130s |
30.885us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
0.800s |
81.070us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.660s |
200.992us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.950s |
90.059us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
2.510s |
111.984us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
2.510s |
111.984us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
2.510s |
111.984us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
2.510s |
111.984us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
2.190s |
492.322us |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
51.130s |
6.617ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
2.290s |
300.104us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
2.290s |
300.104us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
1.190s |
43.315us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
22.190s |
520.945us |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
4.162m |
12.083ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
2.510s |
111.984us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
51.130s |
6.617ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
51.130s |
6.617ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
51.130s |
6.617ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
22.190s |
520.945us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
1.190s |
43.315us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
51.130s |
6.617ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
49.170s |
15.406ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
22.190s |
520.945us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
52.470s |
2.615ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |