PATTGEN Simulation Results

Monday September 29 2025 18:33:12 UTC

GitHub Revision: `8780efb`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	2.000s	53.748us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	51.821us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	1.000s	11.492us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	2.000s	1.845ms	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	1.000s	85.495us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	2.000s	22.015us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.000s	11.492us	1	1	100.00
		pattgen_csr_aliasing	1.000s	85.495us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	1.067m	2.635ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	17.000s	11.395ms	1	1	100.00
V2	error	pattgen_error	1.000s	17.173us	1	1	100.00
V2	stress_all	pattgen_stress_all	3.100m	82.934ms	0	1	0.00
V2	alert_test	pattgen_alert_test	1.000s	21.371us	1	1	100.00
V2	intr_test	pattgen_intr_test	2.000s	23.579us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.000s	69.675us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.000s	69.675us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	51.821us	1	1	100.00
		pattgen_csr_rw	1.000s	11.492us	1	1	100.00
		pattgen_csr_aliasing	1.000s	85.495us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	23.820us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	51.821us	1	1	100.00
		pattgen_csr_rw	1.000s	11.492us	1	1	100.00
		pattgen_csr_aliasing	1.000s	85.495us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	23.820us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	2.000s	150.128us	1	1	100.00
		pattgen_sec_cm	1.000s	271.444us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	2.000s	150.128us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	46.000s	5.556ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	1.000s	25.666us	1	1	100.00
		TOTAL			16	18	88.89

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test pattgen_stress_all_with_rand_reset has 1 failures.

0.pattgen_stress_all_with_rand_reset.48768691772014566697819960074378848540170845935321825334730467747073497952649
Line 182, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2007735349 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 2007736934 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2007736934 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/10
  UVM_INFO @ 2007768185 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all has 1 failures.
  - 0.pattgen_stress_all.25840091954830187059352645637512085290031964389665097849916547737504409007919
    Line 141, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @ 82933855077 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  ------------------------------------
  Name      Type          Size  Value
  ------------------------------------
  exp_item  pattgen_item  -     @11610
```