ROM_CTRL/32KB Simulation Results

Monday September 29 2025 18:33:12 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	4.450s	625.277us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	6.790s	756.062us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	3.870s	2.097ms	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	3.320s	529.040us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	3.790s	129.991us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	4.130s	310.107us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	3.870s	2.097ms	1	1	100.00
		rom_ctrl_csr_aliasing	3.790s	129.991us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	3.170s	728.557us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.230s	535.504us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.390s	186.606us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	11.870s	856.922us	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	6.660s	229.772us	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	3.270s	961.993us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	9.600s	171.513us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	9.600s	171.513us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	6.790s	756.062us	1	1	100.00
		rom_ctrl_csr_rw	3.870s	2.097ms	1	1	100.00
		rom_ctrl_csr_aliasing	3.790s	129.991us	1	1	100.00
		rom_ctrl_same_csr_outstanding	6.460s	167.982us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	6.790s	756.062us	1	1	100.00
		rom_ctrl_csr_rw	3.870s	2.097ms	1	1	100.00
		rom_ctrl_csr_aliasing	3.790s	129.991us	1	1	100.00
		rom_ctrl_same_csr_outstanding	6.460s	167.982us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.179m	7.814ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	27.390s	3.873ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.729m	386.087us	0	1	0.00
		rom_ctrl_tl_intg_err	50.350s	870.747us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.729m	386.087us	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	1.729m	386.087us	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.179m	7.814ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.179m	7.814ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.179m	7.814ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.179m	7.814ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.179m	7.814ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.729m	386.087us	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.729m	386.087us	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	4.450s	625.277us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	4.450s	625.277us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	4.450s	625.277us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	50.350s	870.747us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.179m	7.814ms	1	1	100.00
		rom_ctrl_kmac_err_chk	6.660s	229.772us	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.179m	7.814ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.179m	7.814ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.179m	7.814ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	27.390s	3.873ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.729m	386.087us	0	1	0.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	52.190s	1.575ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.110576480507178469945791463523946979691974642202800062569954168548831691327451
      Line 171, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 6822325ps failed at 6822325ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 6822325ps failed at 6822325ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'