RV_TIMER Simulation Results

Monday September 29 2025 18:33:12 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.800s	99.941us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.810s	60.377us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.620s	14.556us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.020s	288.713us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.930s	33.860us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.970s	125.027us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.620s	14.556us	1	1	100.00
		rv_timer_csr_aliasing	0.930s	33.860us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	5.750s	6.667ms	0	1	0.00
V2	disabled	rv_timer_disabled	1.450s	2.488ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	5.415m	255.936ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	5.415m	255.936ms	1	1	100.00
V2	stress	rv_timer_stress_all	1.640s	295.232us	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.660s	44.734us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.650s	33.340us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.610s	37.958us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.610s	37.958us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.810s	60.377us	1	1	100.00
		rv_timer_csr_rw	0.620s	14.556us	1	1	100.00
		rv_timer_csr_aliasing	0.930s	33.860us	1	1	100.00
		rv_timer_same_csr_outstanding	0.620s	19.192us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.810s	60.377us	1	1	100.00
		rv_timer_csr_rw	0.620s	14.556us	1	1	100.00
		rv_timer_csr_aliasing	0.930s	33.860us	1	1	100.00
		rv_timer_same_csr_outstanding	0.620s	19.192us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.830s	270.347us	1	1	100.00
		rv_timer_tl_intg_err	1.230s	75.507us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.230s	75.507us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.750s	76.349us	0	1	0.00
V3	max_value	rv_timer_max	0.720s	182.269us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	7.420s	2.074ms	1	1	100.00
V3		TOTAL			1	3	33.33
		TOTAL			16	19	84.21

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.19626630088723527087901838359527614502524053030009241301252881695686924469946
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @  76348559 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x1dbfe704) == 0x1
        UVM_INFO @  76348559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.77170891128019832352281043932775438452786611740721308082947861827917955040647
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 6666899280 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x335b7304) == 0x1
        UVM_INFO @ 6666899280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.110775685584941943745469541266002109702221457397356537536556449873900865870738
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @ 182269204 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 182269204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---