SPI_DEVICE/1R1W Simulation Results

Monday September 29 2025 18:33:12 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.271m	17.060ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.860s	39.233us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.910s	95.360us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	8.800s	726.112us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.340s	409.868us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.800s	1.009ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.910s	95.360us	1	1	100.00
		spi_device_csr_aliasing	6.340s	409.868us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.830s	23.771us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.210s	78.322us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.820s	45.563us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.820s	1.551us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.800s	3.880us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.020s	118.572us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.020s	118.572us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.370s	6.620ms	1	1	100.00
		spi_device_tpm_sts_read	0.810s	50.893us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	22.420s	11.347ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	5.980s	2.006ms	1	1	100.00
		spi_device_flash_all	21.330s	8.114ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.950s	3.975ms	1	1	100.00
		spi_device_flash_all	21.330s	8.114ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.950s	3.975ms	1	1	100.00
		spi_device_flash_all	21.330s	8.114ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	21.330s	8.114ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.360s	155.071us	1	1	100.00
		spi_device_flash_all	21.330s	8.114ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.360s	155.071us	1	1	100.00
		spi_device_flash_all	21.330s	8.114ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.360s	155.071us	1	1	100.00
		spi_device_flash_all	21.330s	8.114ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.360s	155.071us	1	1	100.00
		spi_device_flash_all	21.330s	8.114ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.360s	155.071us	1	1	100.00
		spi_device_flash_all	21.330s	8.114ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	12.350s	5.542ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	41.450s	6.906ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	41.450s	6.906ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	41.450s	6.906ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.890s	217.136us	1	1	100.00
		spi_device_read_buffer_direct	7.550s	7.351ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	41.450s	6.906ms	1	1	100.00
		spi_device_flash_all	21.330s	8.114ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	21.330s	8.114ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	21.330s	8.114ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	1.990s	130.422us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	1.990s	130.422us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.271m	17.060ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	6.766m	70.101ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.068m	8.949ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.990s	12.220us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.760s	59.044us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.590s	937.367us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.590s	937.367us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.860s	39.233us	1	1	100.00
		spi_device_csr_rw	1.910s	95.360us	1	1	100.00
		spi_device_csr_aliasing	6.340s	409.868us	1	1	100.00
		spi_device_same_csr_outstanding	3.790s	213.646us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.860s	39.233us	1	1	100.00
		spi_device_csr_rw	1.910s	95.360us	1	1	100.00
		spi_device_csr_aliasing	6.340s	409.868us	1	1	100.00
		spi_device_same_csr_outstanding	3.790s	213.646us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.220s	323.416us	1	1	100.00
		spi_device_tl_intg_err	10.730s	2.232ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	10.730s	2.232ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	59.750s	9.147ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.17009246207463372464634999841992185321618019717339373493018053950919809671486
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1020479 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[16])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1020479 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1020479 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[912])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.108245025028955324150337347022693201600041989344988251444637161137197548781533
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1659326 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9e73b3 [100111100111001110110011] vs 0x0 [0])
        UVM_ERROR @   1741326 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x484d74 [10010000100110101110100] vs 0x0 [0])
        UVM_ERROR @   1823326 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xaa7bf8 [101010100111101111111000] vs 0x0 [0])
        UVM_ERROR @   1842326 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc2cd32 [110000101100110100110010] vs 0x0 [0])
        UVM_ERROR @   1929326 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8cfcfa [100011001111110011111010] vs 0x0 [0])