SPI_DEVICE/2P Simulation Results

Monday September 29 2025 18:33:12 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	50.410s	3.615ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.890s	73.333us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.560s	268.595us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	25.960s	9.315ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.290s	121.328us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.370s	212.574us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.560s	268.595us	1	1	100.00
		spi_device_csr_aliasing	5.290s	121.328us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.740s	16.163us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.470s	122.172us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.860s	16.402us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.930s	143.284us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	0.660s	19.172us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	0.670s	81.027us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	0.670s	81.027us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.490s	2.293ms	1	1	100.00
		spi_device_tpm_sts_read	0.760s	63.197us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	0.700s	30.090us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.910s	1.337ms	1	1	100.00
		spi_device_flash_all	52.030s	19.109ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	7.170s	2.798ms	1	1	100.00
		spi_device_flash_all	52.030s	19.109ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	7.170s	2.798ms	1	1	100.00
		spi_device_flash_all	52.030s	19.109ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	52.030s	19.109ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.840s	419.520us	1	1	100.00
		spi_device_flash_all	52.030s	19.109ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.840s	419.520us	1	1	100.00
		spi_device_flash_all	52.030s	19.109ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.840s	419.520us	1	1	100.00
		spi_device_flash_all	52.030s	19.109ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.840s	419.520us	1	1	100.00
		spi_device_flash_all	52.030s	19.109ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.840s	419.520us	1	1	100.00
		spi_device_flash_all	52.030s	19.109ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	22.830s	50.845ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	4.870s	321.117us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	4.870s	321.117us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	4.870s	321.117us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	7.860s	796.270us	1	1	100.00
		spi_device_read_buffer_direct	9.600s	8.154ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	4.870s	321.117us	1	1	100.00
		spi_device_flash_all	52.030s	19.109ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	52.030s	19.109ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	52.030s	19.109ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	5.250s	927.763us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	5.250s	927.763us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	50.410s	3.615ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.731m	11.820ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.270s	67.996us	1	1	100.00
V2	alert_test	spi_device_alert_test	0.840s	14.338us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.700s	13.633us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.020s	160.339us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.020s	160.339us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.890s	73.333us	1	1	100.00
		spi_device_csr_rw	1.560s	268.595us	1	1	100.00
		spi_device_csr_aliasing	5.290s	121.328us	1	1	100.00
		spi_device_same_csr_outstanding	1.540s	828.001us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.890s	73.333us	1	1	100.00
		spi_device_csr_rw	1.560s	268.595us	1	1	100.00
		spi_device_csr_aliasing	5.290s	121.328us	1	1	100.00
		spi_device_same_csr_outstanding	1.540s	828.001us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	0.870s	113.422us	1	1	100.00
		spi_device_tl_intg_err	5.610s	1.347ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	5.610s	1.347ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	11.520s	803.444us	1	1	100.00
		TOTAL			33	33	100.00