SPI_HOST Simulation Results

Monday September 29 2025 18:33:12 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.083m	7.171ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.000s	46.083us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	25.182us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	902.343us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	23.119us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	32.483us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	25.182us	1	1	100.00
		spi_host_csr_aliasing	2.000s	23.119us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	35.900us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	40.713us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	1.000s	61.460us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.000s	94.138us	1	1	100.00
		spi_host_error_cmd	1.000s	20.056us	1	1	100.00
		spi_host_event	6.000s	425.143us	1	1	100.00
V2	clock_rate	spi_host_speed	2.000s	179.164us	1	1	100.00
V2	speed	spi_host_speed	2.000s	179.164us	1	1	100.00
V2	chip_select_timing	spi_host_speed	2.000s	179.164us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	5.000s	190.489us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	1.000s	27.135us	1	1	100.00
V2	cpol_cpha	spi_host_speed	2.000s	179.164us	1	1	100.00
V2	full_cycle	spi_host_speed	2.000s	179.164us	1	1	100.00
V2	duplex	spi_host_smoke	1.083m	7.171ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	1.083m	7.171ms	1	1	100.00
V2	stress_all	spi_host_stress_all	20.000s	2.022ms	1	1	100.00
V2	spien	spi_host_spien	8.000s	5.526ms	1	1	100.00
V2	stall	spi_host_status_stall	1.350m	7.054ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	2.389ms	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	2.000s	94.138us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	29.530us	1	1	100.00
V2	intr_test	spi_host_intr_test	1.000s	15.732us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	103.117us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	103.117us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.000s	46.083us	1	1	100.00
		spi_host_csr_rw	1.000s	25.182us	1	1	100.00
		spi_host_csr_aliasing	2.000s	23.119us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	37.745us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.000s	46.083us	1	1	100.00
		spi_host_csr_rw	1.000s	25.182us	1	1	100.00
		spi_host_csr_aliasing	2.000s	23.119us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	37.745us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	245.375us	1	1	100.00
		spi_host_sec_cm	2.000s	146.306us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	245.375us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	38.000s	2.154ms	1	1	100.00
		TOTAL			26	26	100.00