SRAM_CTRL/MAIN Simulation Results

Monday September 29 2025 18:33:12 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	17.120s	5.631ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.870s	28.777us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.740s	47.971us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.010s	93.998us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.700s	59.990us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.020s	5.906ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.740s	47.971us	1	1	100.00
		sram_ctrl_csr_aliasing	0.700s	59.990us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.027m	14.423ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.121m	2.630ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	1.510m	5.377ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.738m	55.610ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	33.142m	317.148ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	1.170m	1.815ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	20.640s	5.052ms	1	1	100.00
V2	executable	sram_ctrl_executable	7.829m	59.048ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	11.730s	3.170ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.359m	26.512ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	7.900s	701.757us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	48.540s	844.301us	1	1	100.00
		sram_ctrl_throughput_w_readback	58.910s	1.825ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	2.377m	2.833ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.280s	727.239us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	51.203m	96.281ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.840s	21.801us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.350s	518.209us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.350s	518.209us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.870s	28.777us	1	1	100.00
		sram_ctrl_csr_rw	0.740s	47.971us	1	1	100.00
		sram_ctrl_csr_aliasing	0.700s	59.990us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.100s	253.323us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.870s	28.777us	1	1	100.00
		sram_ctrl_csr_rw	0.740s	47.971us	1	1	100.00
		sram_ctrl_csr_aliasing	0.700s	59.990us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.100s	253.323us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	17.110s	73.753ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.920s	8.109us	0	1	0.00
		sram_ctrl_tl_intg_err	1.540s	192.245us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.920s	8.109us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.540s	192.245us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	2.377m	2.833ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	2.377m	2.833ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.740s	47.971us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.829m	59.048ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.829m	59.048ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.829m	59.048ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	20.640s	5.052ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.160s	3.063ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	17.110s	73.753ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	3.850s	695.608us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	17.120s	5.631ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	17.120s	5.631ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.829m	59.048ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.920s	8.109us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	20.640s	5.052ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.920s	8.109us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.920s	8.109us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	17.120s	5.631ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.920s	8.109us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.091m	8.735ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.77220938118589358812060038128721973222253803835084344223225882973659103275351
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   8108756 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   8108756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---