SRAM_CTRL/RET Simulation Results

Monday September 29 2025 18:33:12 UTC

GitHub Revision: `8780efb`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	10.320s	1.455ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.640s	34.519us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.620s	28.788us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.090s	65.236us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.640s	12.701us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	0.760s	28.760us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.620s	28.788us	1	1	100.00
		sram_ctrl_csr_aliasing	0.640s	12.701us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.770s	182.121us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.970s	89.592us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	12.441m	22.101ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.822m	1.627ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	41.880s	5.226ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	4.213m	7.139ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.520s	1.851ms	1	1	100.00
V2	executable	sram_ctrl_executable	3.572m	16.840ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	13.610s	4.489ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.179m	22.552ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	20.780s	459.797us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	2.190s	51.843us	1	1	100.00
		sram_ctrl_throughput_w_readback	2.610s	72.809us	1	1	100.00
V2	regwen	sram_ctrl_regwen	4.474m	5.069ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.720s	60.271us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	11.944m	32.268ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.650s	17.151us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.450s	35.982us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.450s	35.982us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.640s	34.519us	1	1	100.00
		sram_ctrl_csr_rw	0.620s	28.788us	1	1	100.00
		sram_ctrl_csr_aliasing	0.640s	12.701us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.730s	18.922us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.640s	34.519us	1	1	100.00
		sram_ctrl_csr_rw	0.620s	28.788us	1	1	100.00
		sram_ctrl_csr_aliasing	0.640s	12.701us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.730s	18.922us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.070s	2.674ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.620s	3.578us	0	1	0.00
		sram_ctrl_tl_intg_err	1.830s	720.177us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.620s	3.578us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.830s	720.177us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	4.474m	5.069ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	4.474m	5.069ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.620s	28.788us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.572m	16.840ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.572m	16.840ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.572m	16.840ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.520s	1.851ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.870s	63.334us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.070s	2.674ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.850s	60.698us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	10.320s	1.455ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	10.320s	1.455ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.572m	16.840ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.620s	3.578us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.520s	1.851ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.620s	3.578us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.620s	3.578us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	10.320s	1.455ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.620s	3.578us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	36.720s	1.553ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

Offending 'reqfifo_rvalid' has 1 failures:
- Test sram_ctrl_mubi_enc_err has 1 failures.
  - 0.sram_ctrl_mubi_enc_err.93616358970905847583207345081336409345200645356298311024424629922577116782929
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @  63333682 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @  63333682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:

Test sram_ctrl_sec_cm has 1 failures.

0.sram_ctrl_sec_cm.36019012437569630862580605318717428607963229596407109035996010053642455239862
Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 1893909ps failed at 1893909ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respOpcode_A: started at 1914317ps failed at 1914317ps
      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'