UART Simulation Results

Monday September 29 2025 18:33:12 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.270s	518.993us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.620s	75.836us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.840s	16.290us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.280s	37.914us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.740s	115.904us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.840s	32.468us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.840s	16.290us	1	1	100.00
		uart_csr_aliasing	0.740s	115.904us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	8.710s	42.552ms	1	1	100.00
V2	parity	uart_smoke	1.270s	518.993us	1	1	100.00
		uart_tx_rx	8.710s	42.552ms	1	1	100.00
V2	parity_error	uart_intr	29.000s	29.563ms	1	1	100.00
		uart_rx_parity_err	4.131m	189.916ms	1	1	100.00
V2	watermark	uart_tx_rx	8.710s	42.552ms	1	1	100.00
		uart_intr	29.000s	29.563ms	1	1	100.00
V2	fifo_full	uart_fifo_full	15.760s	186.867ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	53.000s	90.519ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	9.130s	8.870ms	1	1	100.00
V2	rx_frame_err	uart_intr	29.000s	29.563ms	1	1	100.00
V2	rx_break_err	uart_intr	29.000s	29.563ms	1	1	100.00
V2	rx_timeout	uart_intr	29.000s	29.563ms	1	1	100.00
V2	perf	uart_perf	1.155m	7.707ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.770s	9.002ms	1	1	100.00
V2	line_loopback	uart_loopback	3.770s	9.002ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	15.340s	22.259ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	10.430s	31.913ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.560s	3.008ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	20.040s	6.037ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	9.281m	175.412ms	1	1	100.00
V2	stress_all	uart_stress_all	1.214m	66.562ms	1	1	100.00
V2	alert_test	uart_alert_test	0.860s	37.446us	1	1	100.00
V2	intr_test	uart_intr_test	0.760s	18.916us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.140s	199.717us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.140s	199.717us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.620s	75.836us	1	1	100.00
		uart_csr_rw	0.840s	16.290us	1	1	100.00
		uart_csr_aliasing	0.740s	115.904us	1	1	100.00
		uart_same_csr_outstanding	0.840s	25.282us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.620s	75.836us	1	1	100.00
		uart_csr_rw	0.840s	16.290us	1	1	100.00
		uart_csr_aliasing	0.740s	115.904us	1	1	100.00
		uart_same_csr_outstanding	0.840s	25.282us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.110s	205.011us	1	1	100.00
		uart_tl_intg_err	1.210s	601.168us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.210s	601.168us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	23.330s	11.218ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 2 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.10742228459078685831010069577736322374563896933737052999224104832552620800609
      Line 74, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 15916111749 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 15916111749 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 17211489141 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 17211489141 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 18396622517 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
      

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 0.uart_stress_all_with_rand_reset.63145337234031753601809399418629120821207936681123504430490599071255322234949
      Line 118, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7242605424 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 7249438812 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 7254313851 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 7258772220 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_INFO @ 7336897845 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 12/448