CHIP Simulation Results

Monday September 29 2025 18:33:12 UTC

GitHub Revision: `8780efb`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.775m	2.654ms	1	1	100.00
		chip_sw_example_rom	1.116m	2.631ms	1	1	100.00
		chip_sw_example_manufacturer	1.847m	2.973ms	1	1	100.00
		chip_sw_example_concurrency	2.020m	2.925ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.590m	4.453ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.385m	4.377ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	5.545m	5.650ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.193h	29.957ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	43.720s	1.955ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.193h	29.957ms	1	1	100.00
		chip_csr_rw	3.385m	4.377ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.170s	219.589us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.667m	4.610ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.667m	4.610ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.667m	4.610ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.158m	4.437ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.158m	4.437ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.884m	4.195ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.886m	4.245ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.059m	4.124ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	4.884m	4.172ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	4.803m	4.049ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	5.030m	4.575ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.222m	4.836ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.222m	4.836ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.387m	3.097ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.083m	3.135ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.984m	3.907ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	3.693m	4.931ms	1	1	100.00
		chip_tap_straps_testunlock0	6.081m	6.012ms	1	1	100.00
		chip_tap_straps_rma	6.453m	6.296ms	1	1	100.00
		chip_tap_straps_prod	12.956m	12.981ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.280m	2.935ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	13.606m	8.845ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.925m	5.333ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.925m	5.333ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.655m	8.099ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	30.604m	19.185ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.511m	3.635ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.268m	6.200ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	57.832m	18.986ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.533m	2.911ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.472m	6.065ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.214m	2.504ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	25.633m	12.583ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.081m	2.635ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.730m	4.308ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.781m	2.655ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.187m	3.496ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	7.829m	7.467ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.903m	5.867ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.868m	2.765ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.903m	5.867ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.033m	3.140ms	1	1	100.00
		chip_sw_aes_smoketest	2.210m	2.848ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.381m	2.892ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.980m	2.932ms	1	1	100.00
		chip_sw_csrng_smoketest	1.863m	2.520ms	1	1	100.00
		chip_sw_entropy_src_smoketest	15.974m	7.824ms	1	1	100.00
		chip_sw_gpio_smoketest	2.549m	2.485ms	1	1	100.00
		chip_sw_hmac_smoketest	3.542m	3.415ms	1	1	100.00
		chip_sw_kmac_smoketest	2.486m	2.557ms	1	1	100.00
		chip_sw_otbn_smoketest	13.051m	7.168ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.103m	4.982ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.177m	5.129ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.781m	3.543ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.694m	3.227ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.108m	3.234ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.079m	3.025ms	1	1	100.00
		chip_sw_uart_smoketest	2.009m	2.815ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.982m	2.294ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.435m	4.515ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.112h	61.170ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	41.941m	16.164ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.241m	5.006ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.990m	3.665ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.947m	2.634ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.025h	53.953ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.974h	57.022ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	58.110s	2.105ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	58.110s	2.105ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.193h	29.957ms	1	1	100.00
		chip_same_csr_outstanding	21.457m	14.164ms	1	1	100.00
		chip_csr_hw_reset	2.590m	4.453ms	1	1	100.00
		chip_csr_rw	3.385m	4.377ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.193h	29.957ms	1	1	100.00
		chip_same_csr_outstanding	21.457m	14.164ms	1	1	100.00
		chip_csr_hw_reset	2.590m	4.453ms	1	1	100.00
		chip_csr_rw	3.385m	4.377ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	16.050s	261.087us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.760s	49.577us	1	1	100.00
		xbar_smoke_large_delays	1.076m	10.750ms	1	1	100.00
		xbar_smoke_slow_rsp	51.860s	5.389ms	1	1	100.00
		xbar_random_zero_delays	34.340s	624.089us	1	1	100.00
		xbar_random_large_delays	1.113m	11.059ms	1	1	100.00
		xbar_random_slow_rsp	4.040m	28.019ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	8.640s	78.629us	1	1	100.00
		xbar_error_and_unmapped_addr	10.040s	107.989us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	9.400s	121.071us	1	1	100.00
		xbar_error_and_unmapped_addr	10.040s	107.989us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	27.950s	1.104ms	1	1	100.00
		xbar_access_same_device_slow_rsp	1.374m	9.614ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	17.060s	292.949us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	55.800s	1.302ms	1	1	100.00
		xbar_stress_all_with_error	49.300s	2.796ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	51.580s	314.611us	1	1	100.00
		xbar_stress_all_with_reset_error	5.428m	5.734ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	41.941m	16.164ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	29.846m	26.727ms	0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	42.913m	16.332ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	35.589m	12.012ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	42.807m	15.364ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	44.990m	16.510ms	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	44.213m	15.593ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	42.822m	15.009ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	16.880s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	20.110s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	18.500s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	26.710s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	16.620s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	20.810s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	17.360s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	18.800s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	17.600s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	16.670s	10.380us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	17.300s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	16.720s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	18.380s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	16.450s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	23.510s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	17.640s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	17.410s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	18.390s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	21.050s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	21.270s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.670s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.930s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.760s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	17.610s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	17.020s	10.400us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	31.699m	11.489ms	1	1	100.00
		rom_e2e_asm_init_dev	40.868m	15.817ms	1	1	100.00
		rom_e2e_asm_init_prod	42.537m	16.154ms	1	1	100.00
		rom_e2e_asm_init_prod_end	42.000m	15.837ms	1	1	100.00
		rom_e2e_asm_init_rma	42.106m	18.921ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	39.818m	15.605ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	37.967m	14.817ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	39.825m	16.858ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	42.001m	16.087ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	53.811m	34.657ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	53.811m	34.657ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.890m	2.809ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.533m	2.911ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.390m	2.635ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	1.942m	3.020ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	25.288m	12.432ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.298m	3.257ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.991m	4.154ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.187m	5.975ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.147m	5.359ms	1	1	100.00
		chip_plic_all_irqs_10	4.385m	3.505ms	1	1	100.00
		chip_plic_all_irqs_20	6.452m	3.652ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.266m	3.720ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	15.446m	12.269ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.013m	3.327ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.719m	2.835ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.131m	6.784ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.526m	6.747ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.661m	7.983ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.092h	255.249ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.511m	4.424ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.103m	4.982ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.511m	4.424ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.650m	8.261ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.650m	8.261ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.548m	6.920ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.988m	4.805ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.556m	5.411ms	1	1	100.00
		chip_sw_aes_idle	1.942m	3.020ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.640m	3.404ms	1	1	100.00
		chip_sw_kmac_idle	1.526m	2.573ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.365m	3.792ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	2.833m	5.076ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.665m	4.147ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.155m	4.715ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	13.435m	8.852ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.685m	4.061ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.913m	4.914ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.355m	4.003ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.221m	4.973ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.582m	3.818ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.113m	4.849ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.655m	8.099ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	7.984m	11.569ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.355m	4.003ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.221m	4.973ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.511m	3.635ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.268m	6.200ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	57.832m	18.986ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.533m	2.911ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.472m	6.065ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.214m	2.504ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	25.633m	12.583ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.081m	2.635ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.730m	4.308ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.781m	2.655ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.308m	3.436ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.537m	4.323ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.842m	7.401ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	51.968m	24.805ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.820m	3.639ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.209m	2.640ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	12.140m	8.267ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.445m	2.993ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.348m	5.085ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	18.161m	17.271ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	3.154h	133.420ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.655m	8.099ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.874m	4.183ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.988m	3.525ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.187m	5.975ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	14.131m	6.784ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.942m	6.400ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.994m	3.369ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	7.294m	7.568ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.958m	3.358ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	49.084m	17.959ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.100m	3.127ms	1	1	100.00
		chip_sw_edn_entropy_reqs	14.771m	7.063ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.100m	3.127ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.942m	6.400ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.042m	2.168ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	25.466m	19.051ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.768m	4.972ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.268m	6.200ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.802m	4.070ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.511m	3.635ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	53.994m	43.042ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	25.466m	19.051ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.996m	3.615ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	15.717m	9.415ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.593m	4.062ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	53.994m	43.042ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.593m	4.062ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.593m	4.062ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.593m	4.062ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.593m	4.062ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.187m	5.975ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	4.184m	11.941ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.861m	4.941ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.754m	5.659ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.754m	5.659ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.068m	2.706ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.214m	2.504ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.640m	3.404ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.697m	2.760ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.939m	3.891ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.698m	4.652ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.253m	4.639ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.954m	5.233ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.261m	3.909ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	15.717m	9.415ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	25.633m	12.583ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	22.944m	10.580ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	25.288m	12.432ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	48.807m	16.748ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.006m	3.394ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.589m	2.958ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.081m	2.635ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	15.717m	9.415ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	10.832m	12.233ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.817m	2.577ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	10.092m	5.667ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.526m	2.573ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.991m	4.154ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	3.693m	4.931ms	1	1	100.00
		chip_tap_straps_rma	6.453m	6.296ms	1	1	100.00
		chip_tap_straps_prod	12.956m	12.981ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.169m	2.809ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	10.832m	12.233ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	10.832m	12.233ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	10.832m	12.233ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	17.270m	7.920ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.593m	4.062ms	1	1	100.00
		chip_sw_flash_rma_unlocked	53.994m	43.042ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	4.128m	3.231ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.540m	6.324ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.375m	6.378ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.043m	6.551ms	1	1	100.00
		chip_sw_lc_ctrl_transition	10.832m	12.233ms	1	1	100.00
		chip_sw_keymgr_key_derivation	15.717m	9.415ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.610m	8.814ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	5.198m	8.173ms	1	1	100.00
		chip_prim_tl_access	4.184m	11.941ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	7.984m	11.569ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.685m	4.061ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.913m	4.914ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.355m	4.003ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.221m	4.973ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.582m	3.818ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.113m	4.849ms	1	1	100.00
		chip_tap_straps_dev	3.693m	4.931ms	1	1	100.00
		chip_tap_straps_rma	6.453m	6.296ms	1	1	100.00
		chip_tap_straps_prod	12.956m	12.981ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.385m	10.164ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.574m	2.910ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.753m	3.798ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.360m	3.177ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.446m	2.884ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	18.734m	21.810ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.385m	10.164ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	59.622m	48.660ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.043h	46.643ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	8.576m	8.701ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.008h	45.875ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	18.734m	21.810ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.048m	1.870ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.097m	2.836ms	1	1	100.00
		rom_volatile_raw_unlock	50.410s	1.758ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	53.905m	16.876ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	57.832m	18.986ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.556m	5.411ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.556m	5.411ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.556m	5.411ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.507m	3.124ms	0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	10.832m	12.233ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	25.466m	19.051ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.507m	3.124ms	0	1	0.00
		chip_sw_keymgr_key_derivation	15.717m	9.415ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.560m	4.430ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.416m	3.317ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	25.466m	19.051ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.507m	3.124ms	0	1	0.00
		chip_sw_keymgr_key_derivation	15.717m	9.415ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.560m	4.430ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.416m	3.317ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	10.832m	12.233ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	6.365m	5.360ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.169m	2.809ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	4.128m	3.231ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.540m	6.324ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.375m	6.378ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.043m	6.551ms	1	1	100.00
		chip_sw_lc_ctrl_transition	10.832m	12.233ms	1	1	100.00
		chip_prim_tl_access	4.184m	11.941ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.184m	11.941ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	17.133m	9.316ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.942m	9.174ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	15.542m	25.529ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.795m	7.544ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.939m	8.826ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	7.568m	7.497ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	11.840m	19.665ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	15.515m	16.954ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	7.650m	8.261ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	10.642m	11.369ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.293m	4.074ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.942m	9.174ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	2.818m	4.100ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	39.717m	38.745ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.295m	7.107ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.903m	5.369ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	20.149m	22.554ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.440m	6.991ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	17.242m	11.261ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	29.054m	26.744ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	3.063m	3.647ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.187m	5.975ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.610m	8.814ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.610m	8.814ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	17.242m	11.261ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	20.149m	22.554ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.293m	4.074ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.103m	4.982ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.378m	4.577ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	2.974m	3.084ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.136m	3.336ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	15.446m	12.269ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.211m	2.304ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.187m	5.975ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	13.526m	6.747ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.316m	4.813ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.026m	5.003ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.327m	2.741ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.416m	3.317ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	2.974m	3.084ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	2.974m	3.084ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	16.238m	14.410ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	15.833m	13.461ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.378m	4.577ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.615m	4.503ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.002m	4.960ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	6.453m	6.296ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.385m	10.164ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.147m	5.359ms	1	1	100.00
		chip_plic_all_irqs_10	4.385m	3.505ms	1	1	100.00
		chip_plic_all_irqs_20	6.452m	3.652ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.287m	3.033ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.825m	3.113ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	41.941m	16.164ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.554m	6.228ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.702m	2.709ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.839m	3.637ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.383m	3.081ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.560m	4.430ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.730m	4.308ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	7.906m	7.429ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.902m	8.415ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	5.198m	8.173ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.187m	5.975ms	1	1	100.00
		chip_sw_data_integrity_escalation	5.925m	5.333ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.440m	6.991ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	18.152m	22.854ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.078m	2.722ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.635m	3.508ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.415m	4.254ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	18.152m	22.854ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	18.152m	22.854ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	11.810m	11.865ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	11.810m	11.865ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	5.694m	6.027ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	53.811m	34.657ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.102m	2.286ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.664m	2.706ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.294m	3.730ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.778m	3.702ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	19.738m	7.888ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.391h	31.505ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	31.988m	12.598ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.731m	3.068ms	1	1	100.00
V2		TOTAL			235	275	85.45
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.201m	2.919ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.924m	2.898ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.620h	72.405ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.773m	3.774ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	19.712m	11.735ms	1	1	100.00
		rom_e2e_jtag_debug_dev	7.379m	15.118ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.407m	2.608ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	4.027m	5.193ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.824m	3.542ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.463m	3.657ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	10.610s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.705m	4.382ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	5.223m	3.158ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	16.747m	6.955ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	14.817m	6.911ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.490m	2.642ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.977m	4.655ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.432m	2.882ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.337m	5.399ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.885m	5.884ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.521m	4.320ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	17.242m	11.261ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	19.712m	11.735ms	1	1	100.00
		rom_e2e_jtag_debug_dev	7.379m	15.118ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.407m	2.608ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.713m	5.506ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.187m	5.975ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.507h	38.860ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.507h	38.860ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.155m	3.706ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.158m	4.437ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	55.161m	19.316ms	1	1	100.00
V3		TOTAL			19	23	82.61
	Unmapped tests	chip_sival_flash_info_access	2.320m	3.369ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.929m	5.180ms	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	32.231m	30.714ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	3.129m	3.311ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.706m	3.528ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	4.926m	4.435ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	13.722s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.742m	2.645ms	1	1	100.00
		TOTAL			278	326	85.28

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.103844013795591803252560053327151827250568559952787138524662209117037936660658
    Line 479, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.101916516956656388313881197962042084603917881088462063345900930150466834659349
    Line 470, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.69656348102891416285720573921002037721813398983046601435445392959146691687319
    Line 494, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.8138734285975915469950908662517219051771626411356023791319779996920187957527
    Line 514, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.87139035638519094025464935489083333176435048675369210097647798159120333430556
    Line 534, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.51530281172440625887076814141897816304384630339831696987174461753564421553834
    Line 500, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.33839431268161758726767771846985756003182393088469332711885318859990740275958
    Line 497, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.14366301613455805023528908961805690560372536729329429873253875960756977235219
    Line 479, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.88601041941697405798256878642652383175422273748651862072943237664703668377902
    Line 474, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.59198259574662054623076319363505079902378338602556899484992922655980692217851
    Line 502, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.40657230357446922793886740106282497458808752646690178633619139039135148704181
    Line 488, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.95159940953290611218071775987695065228089787346720975329930653147389892061270
    Line 500, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.37719904099171667890511287055194843779653215869705457961212153849361043881200
    Line 548, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.52808007308582886326713625111277628474475923586113032980625697035903768128794
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 2.118s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.5634621590228268658310049375222051423327250701370476083080477635918733808823
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.165s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.69539419865307152799616012782647059607673724892723315802917549474483701653086
    Line 558, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.40860528181038205372519725937065686519281316916234254160207347049674247440854
    Line 466, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.21560475591954995771321300369311188610392184910679083205956587044386603394624
    Line 546, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.21524099067552912344382802542969924269907925009784114024068804969127307134535
    Line 485, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.83270159743383443172236038617257697433830315970298917923787374324382555945608
    Line 401, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2708.816600 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2708.816600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.52914247169471617873547748305455602174792176147849142133526139092939762041100
    Line 461, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 30714.197490 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 30714.197490 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78460) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.100429273126172694935995462804490307482960030575573251842399759506373216816537
Line 417, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3083.896020 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78460) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3083.896020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.40911633509956711206636190497167369727587216519058066780969649366607322693489
    Line 404, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11864.507530 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11864.507530 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.94315824862194935226170484362159414874705655468599201077415123346776242944161
    Line 419, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34657.312202 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34657.312202 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otbn_mem_scramble_test_sim_dv(sw/device/tests/otbn_mem_scramble_test.c:248)] CHECK-fail: Expecting at least * IMEM integrity errors, got * has 1 failures:
- Test chip_sw_otbn_mem_scramble has 1 failures.
  - 0.chip_sw_otbn_mem_scramble.66889608225112358439988041322321953129023357301633386441575659429923486892527
    Line 392, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_mem_scramble/latest/run.log
```
  UVM_ERROR @ 3124.173050 us: (sw_logger_if.sv:526) [otbn_mem_scramble_test_sim_dv(sw/device/tests/otbn_mem_scramble_test.c:248)] CHECK-fail: Expecting at least 48 IMEM integrity errors, got 47
  UVM_INFO @ 3124.173050 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.26807927309694929525595209172542206316177336810025277014340929050735782756198
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3256.918001 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3256.918001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.70614017899739403101618648840188473008660032472857820596292910060123162118215
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2835.442206 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2835.442206 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.46747176236661825755723222776331937882638229150219706425420951261387114824801
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.16230731622825741899744326106223839887259649471002727859873298175401707164058
    Line 397, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2759.669375 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2759.669375 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34432) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.9062186351148367867331990580782185767868132305460741960095270725392476261417
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2105.313866 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34432) { a_addr: 'h10508  a_data: 'h29ce2c9a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h34  a_opcode: 'h4  a_user: 'h18644  d_param: 'h0  d_source: 'h34  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2105.313866 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.56503916561230162782131508610199151599824439901730054510620192799390436070596
    Line 405, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2897.972560 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2897.972560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.68946154089370174376270743687109130366762815787733688841726293794594998522118
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3664.796000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3664.796000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.64453910550021190788950255827713713913182191462354701096138814941789905613251
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 2633.812000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2633.812000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.56686233835386887176518521352809384478205137790149843181424451838737435796871
    Line 416, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 19185.382541 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 19185.382541 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.24847730553889056107501416693390174246071574991596975164784700141624210075245
    Line 453, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3773.928667 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3773.928667 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rom_e2e_shutdown_output_vseq.sv:23) [chip_sw_rom_e2e_shutdown_output_vseq] wait timeout occurred! has 1 failures:
- Test rom_e2e_shutdown_output has 1 failures.
  - 0.rom_e2e_shutdown_output.2432204923525261428357139460326741293963953440197192377693422490578841554048
    Line 458, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log
```
  UVM_FATAL @ 26726.788163 us: (chip_sw_rom_e2e_shutdown_output_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] wait timeout occurred!
  UVM_INFO @ 26726.788163 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:

Test rom_e2e_boot_policy_valid_a_good_b_good_prod has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_prod.53733854238675746840536714588330384346148147856827693391329536129081596772079
Line 468, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log

      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 2356037079ps failed at 2356037079ps
      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 2356281543ps failed at 2356281543ps
      Offending '(pend_req[h2d.a_source].pend == 0)'

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.5220037144976035750762389892541696136041043375217088660129719766578383113509
    Line 492, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.22958106221404867254668062805615595987175623141253419194242789243000124296749
    Line 455, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 1 failures:
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.73074115289477012773116443201974854454849691964522021962840108397530918060071
    Line 450, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 15118.066910 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 15118.066910 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 1 failures:
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.90527144714644096674678222223637170228730964409693346910793977789108844977525
    Line 450, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_ERROR @ 2608.092498 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 2608.092498 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31900) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.40010529792008039105610782735408580947320943106627354117034038684179804131132
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1955.430554 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31900) { a_addr: 'h106cc  a_data: 'h347f9028  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h23  a_opcode: 'h4  a_user: 'h19eb1  d_param: 'h0  d_source: 'h23  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1955.430554 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---