ADC_CTRL Simulation Results

Tuesday September 30 2025 19:18:44 UTC

GitHub Revision: bd069a0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	2.890s	5.962ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.760s	1.318ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.140s	338.232us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	57.220s	24.858ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	1.890s	337.249us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.320s	358.526us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.140s	338.232us	1	1	100.00
		adc_ctrl_csr_aliasing	1.890s	337.249us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	4.771m	324.572ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	4.470m	331.081ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	2.438m	162.394ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	1.462m	331.576ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	3.108m	439.603ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	11.399m	400.508ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	11.881m	408.923ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	45.630s	2.000s	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	9.120s	4.517ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	13.690s	24.011ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	39.160s	63.184ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	48.080s	168.108ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	0.890s	470.161us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	0.900s	389.784us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	1.710s	681.452us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	1.710s	681.452us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.760s	1.318ms	1	1	100.00
		adc_ctrl_csr_rw	1.140s	338.232us	1	1	100.00
		adc_ctrl_csr_aliasing	1.890s	337.249us	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.430s	2.015ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.760s	1.318ms	1	1	100.00
		adc_ctrl_csr_rw	1.140s	338.232us	1	1	100.00
		adc_ctrl_csr_aliasing	1.890s	337.249us	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.430s	2.015ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	4.090s	4.525ms	1	1	100.00
		adc_ctrl_tl_intg_err	16.660s	8.434ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	16.660s	8.434ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	7.320s	4.111ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.58360834798446021940284318262475841540215688276378830515170368918594917236615
      Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---