AES/MASKED Simulation Results

Tuesday September 30 2025 19:18:44 UTC

GitHub Revision: bd069a0

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	195.691us	1	1	100.00
V1	smoke	aes_smoke	2.000s	222.137us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	62.367us	1	1	100.00
V1	csr_rw	aes_csr_rw	1.000s	60.312us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	3.000s	125.754us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	2.000s	181.647us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	69.370us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.000s	60.312us	1	1	100.00
		aes_csr_aliasing	2.000s	181.647us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	2.000s	222.137us	1	1	100.00
		aes_config_error	2.000s	87.245us	1	1	100.00
		aes_stress	2.000s	70.100us	1	1	100.00
V2	key_length	aes_smoke	2.000s	222.137us	1	1	100.00
		aes_config_error	2.000s	87.245us	1	1	100.00
		aes_stress	2.000s	70.100us	1	1	100.00
V2	back2back	aes_stress	2.000s	70.100us	1	1	100.00
		aes_b2b	3.000s	62.134us	1	1	100.00
V2	backpressure	aes_stress	2.000s	70.100us	1	1	100.00
V2	multi_message	aes_smoke	2.000s	222.137us	1	1	100.00
		aes_config_error	2.000s	87.245us	1	1	100.00
		aes_stress	2.000s	70.100us	1	1	100.00
		aes_alert_reset	5.000s	99.128us	1	1	100.00
V2	failure_test	aes_man_cfg_err	3.000s	64.684us	1	1	100.00
		aes_config_error	2.000s	87.245us	1	1	100.00
		aes_alert_reset	5.000s	99.128us	1	1	100.00
V2	trigger_clear_test	aes_clear	4.000s	132.950us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	195.293us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	99.128us	1	1	100.00
V2	stress	aes_stress	2.000s	70.100us	1	1	100.00
V2	sideload	aes_stress	2.000s	70.100us	1	1	100.00
		aes_sideload	3.000s	347.682us	1	1	100.00
V2	deinitialization	aes_deinit	3.000s	195.675us	1	1	100.00
V2	stress_all	aes_stress_all	25.000s	1.890ms	1	1	100.00
V2	alert_test	aes_alert_test	2.000s	52.487us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	2.000s	97.342us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	2.000s	97.342us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	62.367us	1	1	100.00
		aes_csr_rw	1.000s	60.312us	1	1	100.00
		aes_csr_aliasing	2.000s	181.647us	1	1	100.00
		aes_same_csr_outstanding	2.000s	148.017us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	62.367us	1	1	100.00
		aes_csr_rw	1.000s	60.312us	1	1	100.00
		aes_csr_aliasing	2.000s	181.647us	1	1	100.00
		aes_same_csr_outstanding	2.000s	148.017us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	3.000s	438.325us	1	1	100.00
V2S	fault_inject	aes_fi	4.000s	116.905us	1	1	100.00
		aes_control_fi	2.000s	70.198us	1	1	100.00
		aes_cipher_fi	2.000s	76.498us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	2.000s	95.969us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	2.000s	95.969us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	2.000s	95.969us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	2.000s	95.969us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	3.000s	153.995us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	2.508ms	1	1	100.00
		aes_tl_intg_err	2.000s	120.077us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	2.000s	120.077us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	99.128us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	2.000s	95.969us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	2.000s	222.137us	1	1	100.00
		aes_stress	2.000s	70.100us	1	1	100.00
		aes_alert_reset	5.000s	99.128us	1	1	100.00
		aes_core_fi	18.000s	10.012ms	0	1	0.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	2.000s	95.969us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	64.018us	1	1	100.00
		aes_stress	2.000s	70.100us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	2.000s	70.100us	1	1	100.00
		aes_sideload	3.000s	347.682us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	64.018us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	64.018us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	64.018us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	64.018us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	64.018us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	2.000s	70.100us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	2.000s	70.100us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	4.000s	116.905us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	4.000s	116.905us	1	1	100.00
		aes_control_fi	2.000s	70.198us	1	1	100.00
		aes_cipher_fi	2.000s	76.498us	1	1	100.00
		aes_ctr_fi	2.000s	46.337us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	4.000s	116.905us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	4.000s	116.905us	1	1	100.00
		aes_control_fi	2.000s	70.198us	1	1	100.00
		aes_cipher_fi	2.000s	76.498us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	2.000s	76.498us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	4.000s	116.905us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	4.000s	116.905us	1	1	100.00
		aes_control_fi	2.000s	70.198us	1	1	100.00
		aes_ctr_fi	2.000s	46.337us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	4.000s	116.905us	1	1	100.00
		aes_control_fi	2.000s	70.198us	1	1	100.00
		aes_cipher_fi	2.000s	76.498us	1	1	100.00
		aes_ctr_fi	2.000s	46.337us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	99.128us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	4.000s	116.905us	1	1	100.00
		aes_control_fi	2.000s	70.198us	1	1	100.00
		aes_cipher_fi	2.000s	76.498us	1	1	100.00
		aes_ctr_fi	2.000s	46.337us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	4.000s	116.905us	1	1	100.00
		aes_control_fi	2.000s	70.198us	1	1	100.00
		aes_cipher_fi	2.000s	76.498us	1	1	100.00
		aes_ctr_fi	2.000s	46.337us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	4.000s	116.905us	1	1	100.00
		aes_control_fi	2.000s	70.198us	1	1	100.00
		aes_ctr_fi	2.000s	46.337us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	4.000s	116.905us	1	1	100.00
		aes_control_fi	2.000s	70.198us	1	1	100.00
		aes_cipher_fi	2.000s	76.498us	1	1	100.00
V2S		TOTAL			10	11	90.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	22.000s	1.007ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			30	32	93.75

Failure Buckets

• UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:

  • Test aes_core_fi has 1 failures.

    • 0.aes_core_fi.102593137916736866605002522366982549164573676126492334063989508137879808062013
      Line 138, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_core_fi/latest/run.log

        UVM_FATAL @ 10012078946 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
        UVM_INFO @ 10012078946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.21035911658467074202864998349264989772864163391530490517590798838059735109062
      Line 858, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 1007434566 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
        UVM_INFO @ 1007434566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---