HMAC Simulation Results

Tuesday September 30 2025 19:18:44 UTC

GitHub Revision: bd069a0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 1.450s 115.443us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.030s 64.403us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.830s 111.624us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 10.210s 312.578us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 2.370s 200.618us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.730s 65.188us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.830s 111.624us 1 1 100.00
hmac_csr_aliasing 2.370s 200.618us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 1.047m 32.215ms 1 1 100.00
V2 back_pressure hmac_back_pressure 39.850s 4.028ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.150s 171.845us 1 1 100.00
hmac_test_sha384_vectors 19.520s 437.560us 1 1 100.00
hmac_test_sha512_vectors 5.848m 43.694ms 1 1 100.00
hmac_test_hmac256_vectors 9.770s 4.394ms 1 1 100.00
hmac_test_hmac384_vectors 6.880s 236.137us 1 1 100.00
hmac_test_hmac512_vectors 9.330s 482.911us 1 1 100.00
V2 burst_wr hmac_burst_wr 27.940s 35.121ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 3.142m 4.261ms 1 1 100.00
V2 error hmac_error 23.240s 603.275us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 55.670s 6.144ms 1 1 100.00
V2 save_and_restore hmac_smoke 1.450s 115.443us 1 1 100.00
hmac_long_msg 1.047m 32.215ms 1 1 100.00
hmac_back_pressure 39.850s 4.028ms 1 1 100.00
hmac_datapath_stress 3.142m 4.261ms 1 1 100.00
hmac_burst_wr 27.940s 35.121ms 1 1 100.00
hmac_stress_all 23.494m 206.546ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 1.450s 115.443us 1 1 100.00
hmac_long_msg 1.047m 32.215ms 1 1 100.00
hmac_back_pressure 39.850s 4.028ms 1 1 100.00
hmac_datapath_stress 3.142m 4.261ms 1 1 100.00
hmac_wipe_secret 55.670s 6.144ms 1 1 100.00
hmac_test_sha256_vectors 8.150s 171.845us 1 1 100.00
hmac_test_sha384_vectors 19.520s 437.560us 1 1 100.00
hmac_test_sha512_vectors 5.848m 43.694ms 1 1 100.00
hmac_test_hmac256_vectors 9.770s 4.394ms 1 1 100.00
hmac_test_hmac384_vectors 6.880s 236.137us 1 1 100.00
hmac_test_hmac512_vectors 9.330s 482.911us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 1.450s 115.443us 1 1 100.00
hmac_long_msg 1.047m 32.215ms 1 1 100.00
hmac_back_pressure 39.850s 4.028ms 1 1 100.00
hmac_datapath_stress 3.142m 4.261ms 1 1 100.00
hmac_burst_wr 27.940s 35.121ms 1 1 100.00
hmac_error 23.240s 603.275us 1 1 100.00
hmac_wipe_secret 55.670s 6.144ms 1 1 100.00
hmac_test_sha256_vectors 8.150s 171.845us 1 1 100.00
hmac_test_sha384_vectors 19.520s 437.560us 1 1 100.00
hmac_test_sha512_vectors 5.848m 43.694ms 1 1 100.00
hmac_test_hmac256_vectors 9.770s 4.394ms 1 1 100.00
hmac_test_hmac384_vectors 6.880s 236.137us 1 1 100.00
hmac_test_hmac512_vectors 9.330s 482.911us 1 1 100.00
hmac_stress_all 23.494m 206.546ms 1 1 100.00
V2 stress_all hmac_stress_all 23.494m 206.546ms 1 1 100.00
V2 alert_test hmac_alert_test 0.870s 15.234us 1 1 100.00
V2 intr_test hmac_intr_test 0.850s 12.076us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.820s 538.334us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.820s 538.334us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.030s 64.403us 1 1 100.00
hmac_csr_rw 0.830s 111.624us 1 1 100.00
hmac_csr_aliasing 2.370s 200.618us 1 1 100.00
hmac_same_csr_outstanding 2.140s 155.049us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.030s 64.403us 1 1 100.00
hmac_csr_rw 0.830s 111.624us 1 1 100.00
hmac_csr_aliasing 2.370s 200.618us 1 1 100.00
hmac_same_csr_outstanding 2.140s 155.049us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.130s 161.545us 1 1 100.00
hmac_tl_intg_err 1.680s 968.300us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 1.680s 968.300us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 1.450s 115.443us 1 1 100.00
V3 stress_reset hmac_stress_reset 5.930s 286.091us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 18.940s 4.790ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.040s 36.189us 1 1 100.00
TOTAL 28 28 100.00