I2C Simulation Results

Tuesday September 30 2025 19:18:44 UTC

GitHub Revision: bd069a0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	22.690s	7.527ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	19.780s	940.813us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.710s	33.631us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.810s	160.952us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.210s	970.462us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.680s	98.094us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.140s	94.729us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.810s	160.952us	1	1	100.00
		i2c_csr_aliasing	1.680s	98.094us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.540s	180.997us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	10.242m	24.316ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	34.410s	4.919ms	1	1	100.00
V2	host_override	i2c_host_override	0.800s	28.461us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	54.800s	3.189ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	22.870s	1.418ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.410s	440.736us	1	1	100.00
		i2c_host_fifo_fmt_empty	15.070s	411.336us	1	1	100.00
		i2c_host_fifo_reset_rx	3.680s	135.292us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	40.320s	5.381ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	9.750s	2.383ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.770s	16.230us	0	1	0.00
V2	target_glitch	i2c_target_glitch	1.820s	489.145us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	2.135m	30.449ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.870s	641.189us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	43.270s	1.773ms	1	1	100.00
		i2c_target_intr_smoke	5.270s	3.387ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.100s	291.156us	1	1	100.00
		i2c_target_fifo_reset_tx	1.200s	179.412us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.637m	38.798ms	1	1	100.00
		i2c_target_stress_rd	43.270s	1.773ms	1	1	100.00
		i2c_target_intr_stress_wr	13.640s	34.016ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.840s	6.602ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	2.230s	514.680us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.640s	820.287us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	21.170s	10.177ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.750s	376.390us	1	1	100.00
		i2c_target_fifo_watermarks_tx	0.980s	177.183us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	34.410s	4.919ms	1	1	100.00
		i2c_host_perf_precise	2.300s	238.259us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	9.750s	2.383ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	1.370s	59.406us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.310s	1.034ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.140s	3.082ms	1	1	100.00
		i2c_target_nack_txstretch	1.440s	132.077us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	5.990s	531.284us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.740s	3.578ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.670s	38.450us	1	1	100.00
V2	intr_test	i2c_intr_test	0.790s	21.447us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.350s	342.803us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.350s	342.803us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.710s	33.631us	1	1	100.00
		i2c_csr_rw	0.810s	160.952us	1	1	100.00
		i2c_csr_aliasing	1.680s	98.094us	1	1	100.00
		i2c_same_csr_outstanding	0.890s	211.983us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.710s	33.631us	1	1	100.00
		i2c_csr_rw	0.810s	160.952us	1	1	100.00
		i2c_csr_aliasing	1.680s	98.094us	1	1	100.00
		i2c_same_csr_outstanding	0.890s	211.983us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	1.410s	178.270us	1	1	100.00
		i2c_sec_cm	0.980s	121.719us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.410s	178.270us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	4.780s	1.611ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.720s	169.039us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	4.270s	673.671us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.50578085003729861377585466793188870630230894437356453864193249585352028890492
      Line 123, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @ 180997017 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 180997017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.54886738148760446435035101841268440301428483808399568566273642774609465893721
      Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @  16230128 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  16230128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.38866264698796572204446916287162208698030487722862244046449866843897887384925
      Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1610883826 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1610883826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.102934809485250548183154749371378159948890657532015540582526143600462523843802
      Line 89, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 673671026 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 673671026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.34576449256140990534910553744975670408708864764742033765950003584187201744376
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 489144876 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 489144876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.97781571422208161524980280517623402787902779845502057008754785770790367473791
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

            Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
        UVM_ERROR @ 169039385 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
        UVM_INFO @ 169039385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.37734078678516477610600618800004486025066087134347639303829958625314463445848
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10176883176 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10176883176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---