KEYMGR Simulation Results

Tuesday September 30 2025 19:18:44 UTC

GitHub Revision: bd069a0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 2.040s 292.220us 1 1 100.00
V1 random keymgr_random 14.600s 1.126ms 1 1 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.170s 120.610us 1 1 100.00
V1 csr_rw keymgr_csr_rw 0.940s 21.581us 1 1 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 4.220s 520.686us 1 1 100.00
V1 csr_aliasing keymgr_csr_aliasing 10.960s 1.168ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.030s 31.601us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 0.940s 21.581us 1 1 100.00
keymgr_csr_aliasing 10.960s 1.168ms 1 1 100.00
V1 TOTAL 7 7 100.00
V2 cfgen_during_op keymgr_cfg_regwen 2.610s 331.289us 1 1 100.00
V2 sideload keymgr_sideload 1.780s 32.077us 1 1 100.00
keymgr_sideload_kmac 40.290s 30.748ms 1 1 100.00
keymgr_sideload_aes 2.870s 272.919us 1 1 100.00
keymgr_sideload_otbn 1.830s 39.880us 1 1 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 2.060s 91.983us 1 1 100.00
V2 lc_disable keymgr_lc_disable 4.560s 226.287us 1 1 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 1.340s 253.975us 1 1 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 5.580s 370.587us 1 1 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 2.260s 341.614us 1 1 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 2.390s 373.064us 1 1 100.00
V2 stress_all keymgr_stress_all 9.960s 427.149us 1 1 100.00
V2 intr_test keymgr_intr_test 0.650s 10.325us 1 1 100.00
V2 alert_test keymgr_alert_test 0.770s 13.087us 1 1 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 3.420s 261.639us 1 1 100.00
V2 tl_d_illegal_access keymgr_tl_errors 3.420s 261.639us 1 1 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.170s 120.610us 1 1 100.00
keymgr_csr_rw 0.940s 21.581us 1 1 100.00
keymgr_csr_aliasing 10.960s 1.168ms 1 1 100.00
keymgr_same_csr_outstanding 1.280s 84.979us 1 1 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.170s 120.610us 1 1 100.00
keymgr_csr_rw 0.940s 21.581us 1 1 100.00
keymgr_csr_aliasing 10.960s 1.168ms 1 1 100.00
keymgr_same_csr_outstanding 1.280s 84.979us 1 1 100.00
V2 TOTAL 16 16 100.00
V2S sec_cm_additional_check keymgr_sec_cm 8.930s 918.901us 1 1 100.00
V2S tl_intg_err keymgr_sec_cm 8.930s 918.901us 1 1 100.00
keymgr_tl_intg_err 3.170s 415.663us 1 1 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 1.520s 89.413us 1 1 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 1.520s 89.413us 1 1 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 1.520s 89.413us 1 1 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 1.520s 89.413us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 6.790s 385.799us 1 1 100.00
V2S prim_count_check keymgr_sec_cm 8.930s 918.901us 1 1 100.00
V2S prim_fsm_check keymgr_sec_cm 8.930s 918.901us 1 1 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 3.170s 415.663us 1 1 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 1.520s 89.413us 1 1 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 2.610s 331.289us 1 1 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 14.600s 1.126ms 1 1 100.00
keymgr_csr_rw 0.940s 21.581us 1 1 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 14.600s 1.126ms 1 1 100.00
keymgr_csr_rw 0.940s 21.581us 1 1 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 14.600s 1.126ms 1 1 100.00
keymgr_csr_rw 0.940s 21.581us 1 1 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 4.560s 226.287us 1 1 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 2.260s 341.614us 1 1 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 2.260s 341.614us 1 1 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 14.600s 1.126ms 1 1 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 1.960s 54.529us 1 1 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 8.930s 918.901us 1 1 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 8.930s 918.901us 1 1 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 8.930s 918.901us 1 1 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 2.840s 600.710us 1 1 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 4.560s 226.287us 1 1 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 8.930s 918.901us 1 1 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 8.930s 918.901us 1 1 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 8.930s 918.901us 1 1 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 2.840s 600.710us 1 1 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 2.840s 600.710us 1 1 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 8.930s 918.901us 1 1 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 2.840s 600.710us 1 1 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 8.930s 918.901us 1 1 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 2.840s 600.710us 1 1 100.00
V2S TOTAL 6 6 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 4.940s 235.244us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 30 100.00