KMAC/UNMASKED Simulation Results

Tuesday September 30 2025 19:18:44 UTC

GitHub Revision: bd069a0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	17.140s	1.453ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.180s	202.918us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.900s	21.318us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.610s	933.955us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.260s	389.298us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.690s	769.697us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.900s	21.318us	1	1	100.00
		kmac_csr_aliasing	6.260s	389.298us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.690s	20.617us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.170s	29.221us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	40.878m	81.880ms	1	1	100.00
V2	burst_write	kmac_burst_write	5.056m	36.943ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	24.990s	2.679ms	1	1	100.00
		kmac_test_vectors_sha3_256	23.310s	2.328ms	1	1	100.00
		kmac_test_vectors_sha3_384	16.060s	434.355us	1	1	100.00
		kmac_test_vectors_sha3_512	10.370s	308.567us	1	1	100.00
		kmac_test_vectors_shake_128	2.163m	14.261ms	1	1	100.00
		kmac_test_vectors_shake_256	5.066m	93.513ms	1	1	100.00
		kmac_test_vectors_kmac	2.130s	83.527us	1	1	100.00
		kmac_test_vectors_kmac_xof	1.850s	59.308us	1	1	100.00
V2	sideload	kmac_sideload	2.010m	13.009ms	1	1	100.00
V2	app	kmac_app	1.250m	8.687ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.679m	23.541ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.082m	17.358ms	1	1	100.00
V2	error	kmac_error	52.110s	4.238ms	1	1	100.00
V2	key_error	kmac_key_error	5.060s	1.229ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	22.320s	10.164ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	17.430s	743.654us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.790s	515.865us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	21.920s	11.020ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.200s	43.304us	1	1	100.00
V2	stress_all	kmac_stress_all	7.548m	21.194ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.720s	14.017us	1	1	100.00
V2	alert_test	kmac_alert_test	0.840s	34.124us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.130s	49.803us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.130s	49.803us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.180s	202.918us	1	1	100.00
		kmac_csr_rw	0.900s	21.318us	1	1	100.00
		kmac_csr_aliasing	6.260s	389.298us	1	1	100.00
		kmac_same_csr_outstanding	1.750s	40.254us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.180s	202.918us	1	1	100.00
		kmac_csr_rw	0.900s	21.318us	1	1	100.00
		kmac_csr_aliasing	6.260s	389.298us	1	1	100.00
		kmac_same_csr_outstanding	1.750s	40.254us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.730s	94.130us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.730s	94.130us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.730s	94.130us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.730s	94.130us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.620s	312.387us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.043m	13.567ms	1	1	100.00
		kmac_tl_intg_err	1.940s	62.272us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.940s	62.272us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.200s	43.304us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	17.140s	1.453ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.010m	13.009ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.730s	94.130us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.043m	13.567ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.043m	13.567ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.043m	13.567ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	17.140s	1.453ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.200s	43.304us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.043m	13.567ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.463m	29.146ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	17.140s	1.453ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.274m	11.744ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.96243892347935171537362158115643986485253953463302132736676774732138568695781
      Line 81, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10163912228 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xdba3c000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
        UVM_INFO @ 10163912228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---