OTBN Simulation Results

Tuesday September 30 2025 19:18:44 UTC

GitHub Revision: bd069a0

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 11.000s 157.721us 0 1 0.00
V1 single_binary otbn_single 9.000s 89.053us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 4.000s 37.568us 1 1 100.00
V1 csr_rw otbn_csr_rw 3.000s 42.799us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 7.000s 433.376us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 4.000s 19.146us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 4.000s 44.884us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 3.000s 42.799us 1 1 100.00
otbn_csr_aliasing 4.000s 19.146us 1 1 100.00
V1 mem_walk otbn_mem_walk 23.000s 1.158ms 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 18.000s 1.777ms 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 28.000s 322.259us 0 1 0.00
V2 multi_error otbn_multi_err 36.000s 169.497us 0 1 0.00
V2 back_to_back otbn_multi 23.000s 56.231us 0 1 0.00
V2 stress_all otbn_stress_all 20.000s 175.944us 0 1 0.00
V2 lc_escalation otbn_escalate 7.000s 26.240us 1 1 100.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 4.000s 30.094us 1 1 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 6.000s 33.062us 0 1 0.00
V2 alert_test otbn_alert_test 4.000s 17.174us 1 1 100.00
V2 intr_test otbn_intr_test 4.000s 39.687us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 5.000s 88.750us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 5.000s 88.750us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 4.000s 37.568us 1 1 100.00
otbn_csr_rw 3.000s 42.799us 1 1 100.00
otbn_csr_aliasing 4.000s 19.146us 1 1 100.00
otbn_same_csr_outstanding 3.000s 146.777us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 4.000s 37.568us 1 1 100.00
otbn_csr_rw 3.000s 42.799us 1 1 100.00
otbn_csr_aliasing 4.000s 19.146us 1 1 100.00
otbn_same_csr_outstanding 3.000s 146.777us 1 1 100.00
V2 TOTAL 6 11 54.55
V2S mem_integrity otbn_imem_err 5.000s 79.842us 0 1 0.00
otbn_dmem_err 8.000s 25.198us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 6.000s 19.829us 0 1 0.00
otbn_controller_ispr_rdata_err 4.000s 17.743us 0 1 0.00
otbn_mac_bignum_acc_err 9.000s 23.794us 0 1 0.00
otbn_urnd_err 6.000s 14.574us 0 1 0.00
V2S illegal_bus_access otbn_illegal_mem_acc 6.000s 48.159us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 5.000s 147.573us 0 1 0.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 4.000s 38.653us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 1.383m 1.812ms 1 1 100.00
otbn_tl_intg_err 9.000s 128.649us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 20.000s 414.244us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 1.383m 1.812ms 1 1 100.00
V2S prim_count_check otbn_sec_cm 1.383m 1.812ms 1 1 100.00
V2S sec_cm_mem_scramble otbn_smoke 11.000s 157.721us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 8.000s 25.198us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 5.000s 79.842us 0 1 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 9.000s 128.649us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 7.000s 26.240us 1 1 100.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 5.000s 79.842us 0 1 0.00
otbn_dmem_err 8.000s 25.198us 0 1 0.00
otbn_zero_state_err_urnd 4.000s 30.094us 1 1 100.00
otbn_illegal_mem_acc 6.000s 48.159us 1 1 100.00
otbn_sec_cm 1.383m 1.812ms 1 1 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 1.383m 1.812ms 1 1 100.00
V2S sec_cm_scramble_key_sideload otbn_single 9.000s 89.053us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 5.000s 79.842us 0 1 0.00
otbn_dmem_err 8.000s 25.198us 0 1 0.00
otbn_zero_state_err_urnd 4.000s 30.094us 1 1 100.00
otbn_illegal_mem_acc 6.000s 48.159us 1 1 100.00
otbn_sec_cm 1.383m 1.812ms 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 1.383m 1.812ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 7.000s 26.240us 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 5.000s 79.842us 0 1 0.00
otbn_dmem_err 8.000s 25.198us 0 1 0.00
otbn_zero_state_err_urnd 4.000s 30.094us 1 1 100.00
otbn_illegal_mem_acc 6.000s 48.159us 1 1 100.00
otbn_sec_cm 1.383m 1.812ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 1.383m 1.812ms 1 1 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 9.000s 89.053us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 7.000s 24.556us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 7.000s 24.895us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 14.000s 97.659us 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 14.000s 97.659us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 17.000s 81.152us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 1.383m 1.812ms 1 1 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 1.383m 1.812ms 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 7.000s 54.502us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 1.383m 1.812ms 1 1 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 1.383m 1.812ms 1 1 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 9.000s 36.520us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 9.000s 36.520us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 6.000s 17.569us 1 1 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 9.000s 89.053us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 9.000s 89.053us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 9.000s 89.053us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 23.000s 56.231us 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 9.000s 89.053us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 9.000s 89.053us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 5.000s 33.067us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 9.000s 89.053us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 1.383m 1.812ms 1 1 100.00
V2S TOTAL 7 20 35.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 4.633m 4.175ms 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 41 48.78

Failure Buckets