PATTGEN Simulation Results

Tuesday September 30 2025 19:18:44 UTC

GitHub Revision: bd069a0

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	2.000s	380.034us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	41.748us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	1.000s	12.287us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	2.000s	1.549ms	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	1.000s	220.114us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	1.000s	47.820us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.000s	12.287us	1	1	100.00
		pattgen_csr_aliasing	1.000s	220.114us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	1.000s	57.086us	1	1	100.00
V2	cnt_rollover	cnt_rollover	1.050m	2.633ms	1	1	100.00
V2	error	pattgen_error	1.000s	76.271us	1	1	100.00
V2	stress_all	pattgen_stress_all	1.883h	2.359s	0	1	0.00
V2	alert_test	pattgen_alert_test	1.000s	21.921us	1	1	100.00
V2	intr_test	pattgen_intr_test	2.000s	69.548us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.000s	24.911us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.000s	24.911us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	41.748us	1	1	100.00
		pattgen_csr_rw	1.000s	12.287us	1	1	100.00
		pattgen_csr_aliasing	1.000s	220.114us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	188.198us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	41.748us	1	1	100.00
		pattgen_csr_rw	1.000s	12.287us	1	1	100.00
		pattgen_csr_aliasing	1.000s	220.114us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	188.198us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	2.000s	53.486us	1	1	100.00
		pattgen_sec_cm	1.000s	547.920us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	2.000s	53.486us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	11.000s	4.841ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	27.000s	10.027ms	0	1	0.00
		TOTAL			15	18	83.33

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:

  • Test pattgen_inactive_level has 1 failures.

    • 0.pattgen_inactive_level.68233694914887372577500422296270348551118633645175102741002781734977401887665
      Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log

        UVM_FATAL @ 10026775828 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x494a6090, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
        UVM_INFO @ 10026775828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.103233155597103556911007939264020384669649063529448279852109709313263240350131
      Line 187, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1952943274 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 1952969212 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1952969212 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 3/5
        UVM_INFO @ 1953209212 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
      

• UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:

  • Test pattgen_stress_all has 1 failures.

    • 0.pattgen_stress_all.92956497299353909263597957714980673781269788245033180613984197927488892622010
      Line 137, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log

        UVM_ERROR @ 2359451125537 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
        ------------------------------------
        Name      Type          Size  Value
        ------------------------------------
        exp_item  pattgen_item  -     @10094