ROM_CTRL/32KB Simulation Results

Tuesday September 30 2025 19:18:44 UTC

GitHub Revision: bd069a0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.280s	186.355us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	5.320s	382.190us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	3.810s	371.589us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	4.590s	166.321us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	4.010s	386.294us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	4.630s	172.890us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	3.810s	371.589us	1	1	100.00
		rom_ctrl_csr_aliasing	4.010s	386.294us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	3.140s	371.215us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.410s	179.662us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.070s	176.920us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	10.240s	330.399us	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	7.750s	327.223us	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	3.260s	386.698us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	6.840s	167.548us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	6.840s	167.548us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	5.320s	382.190us	1	1	100.00
		rom_ctrl_csr_rw	3.810s	371.589us	1	1	100.00
		rom_ctrl_csr_aliasing	4.010s	386.294us	1	1	100.00
		rom_ctrl_same_csr_outstanding	3.800s	534.315us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	5.320s	382.190us	1	1	100.00
		rom_ctrl_csr_rw	3.810s	371.589us	1	1	100.00
		rom_ctrl_csr_aliasing	4.010s	386.294us	1	1	100.00
		rom_ctrl_same_csr_outstanding	3.800s	534.315us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	48.340s	1.519ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	14.040s	2.974ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.318m	1.697ms	0	1	0.00
		rom_ctrl_tl_intg_err	24.160s	401.346us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.318m	1.697ms	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.318m	1.697ms	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	48.340s	1.519ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	48.340s	1.519ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	48.340s	1.519ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	48.340s	1.519ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	48.340s	1.519ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.318m	1.697ms	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.318m	1.697ms	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.280s	186.355us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.280s	186.355us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.280s	186.355us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	24.160s	401.346us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	48.340s	1.519ms	1	1	100.00
		rom_ctrl_kmac_err_chk	7.750s	327.223us	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	48.340s	1.519ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	48.340s	1.519ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	48.340s	1.519ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	14.040s	2.974ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.318m	1.697ms	0	1	0.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	4.917m	4.378ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.97878868752781365497503777762038975258057583271453124462218203430705657049598
      Line 106, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 4173328ps failed at 4173328ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 4173328ps failed at 4173328ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'